tangxifan
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0b49c22682
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
tangxifan
|
4b8f5f294a
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[Tool] Capsulate fabric bitstream organization for configuration chain
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2021-04-10 14:28:31 -06:00 |
tangxifan
|
afa0e751da
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[Tool] Use alias for complex bitstream data types
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2021-04-10 14:12:02 -06:00 |
tangxifan
|
d877a02534
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
tangxifan
|
85640a7403
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[Tool] Extend bitstream setting to support mode bits overload from eblif file
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2021-03-10 20:45:48 -07:00 |
tangxifan
|
a5b8b2a64a
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[Tool] Use dedicated function to identify wire LUT created by repacker
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2021-02-18 19:37:44 -07:00 |
tangxifan
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aae03482f5
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[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
tangxifan
|
0c409b5bcc
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[Tool] Add bitstream annotation support
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2021-02-01 20:49:36 -07:00 |
tangxifan
|
9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
tangxifan
|
4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
tangxifan
|
3f91b8433e
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
tangxifan
|
372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
tangxifan
|
e627b6dd5d
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[Tool] Enhance port attribute checks in tile annotation data structure
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2020-11-11 13:41:05 -07:00 |
tangxifan
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9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
tangxifan
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dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
tangxifan
|
5fe9c27600
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[Tool] Remove redundant assertation
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2020-11-09 09:42:39 -07:00 |
tangxifan
|
ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
tangxifan
|
9b0617ffe6
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[Tool] Bug fix for mappable I/O support
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2020-11-04 20:45:51 -07:00 |
tangxifan
|
37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
tangxifan
|
4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
tangxifan
|
b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
tangxifan
|
5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
tangxifan
|
987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
tangxifan
|
448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
tangxifan
|
e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
tangxifan
|
222bc86cbf
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
|
2020-09-20 12:53:28 -06:00 |
tangxifan
|
04070fd4ca
|
[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
tangxifan
|
a4a38f8156
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support multi-bit power gate ports in FPGA-SPICE
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2020-07-22 20:04:39 -06:00 |
tangxifan
|
f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
tangxifan
|
824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
tangxifan
|
83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
tangxifan
|
033c92c365
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precisely reserve memory for child blocks in bitstream manager
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2020-07-03 22:47:21 -06:00 |
tangxifan
|
57e6c84252
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add reserve net sources and sinks to module manager
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2020-06-29 22:49:11 -06:00 |
tangxifan
|
66746f69da
|
optimizing memory efficiency by reserving nets in module manager
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2020-06-29 21:27:43 -06:00 |
tangxifan
|
5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
tangxifan
|
0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
tangxifan
|
fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
|
2020-06-11 19:31:13 -06:00 |
tangxifan
|
fbe05963e0
|
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
|
2020-06-11 19:31:12 -06:00 |
tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
|
2020-06-11 19:31:10 -06:00 |
tangxifan
|
bf9f62f0f7
|
keep bug fixing for frame-based configuration protocol.
|
2020-06-11 19:31:10 -06:00 |
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
tangxifan
|
c696e3d20f
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refine frame-based memory addition to compact the area
|
2020-06-11 19:31:09 -06:00 |
tangxifan
|
290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
|
2020-06-11 19:31:09 -06:00 |
tangxifan
|
8864920460
|
add frame-based memory module builder
|
2020-06-11 19:31:09 -06:00 |
tangxifan
|
3a26bb5eef
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add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
|
2020-06-11 19:31:07 -06:00 |
tangxifan
|
bf841b9a8e
|
bug fixed in identifying wired LUT
|
2020-04-22 17:28:16 -06:00 |