Commit Graph

9 Commits

Author SHA1 Message Date
tangxifan 62853c092f refactoring local encoders. Ready to plug in 2019-09-10 15:16:29 -06:00
tangxifan e623c19055 implementing mux Verilog generation. Bugs detected, fixing ongoing 2019-09-04 23:54:53 -06:00
tangxifan fe7dfd59c3 Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-24 23:54:37 -06:00
tangxifan 27b619554d add stats for verilog modules 2019-08-23 20:23:42 -06:00
tangxifan ad06e9c98c plug in module manager 2019-08-23 20:23:41 -06:00
tangxifan fcb31e4c24 add stats for verilog modules 2019-08-23 18:41:16 -06:00
tangxifan 8eebca9daa plug in module manager 2019-08-23 17:39:29 -06:00
tangxifan 931b042750 refactoring module manager 2019-08-23 12:52:01 -06:00
tangxifan 732e24767f developing module manager 2019-08-22 23:49:35 -06:00