4 Commits

Author	SHA1	Message	Date
tangxifan	5cb3717433	add single mode test case to regression test. debugging now	2019-10-28 15:57:17 -06:00
tangxifan	4e7af5cdc5	update tileable_routing test	2019-09-18 15:59:32 -06:00
tangxifan	d7ac7d3649	start refactoring the switch block verilog generation	2019-09-17 20:40:26 -06:00
tangxifan	5abbfd6a0f	add tileable routing to regression test	2019-09-16 20:45:02 -06:00