tangxifan
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6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
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6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
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721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
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tangxifan
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0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
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2e7684b746
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adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
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2ef083c49d
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adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
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bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
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7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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2020-03-03 12:29:58 -07:00 |
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tangxifan
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e37ac8a098
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
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072965cd64
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |