6 Commits

Author	SHA1	Message	Date
tangxifan	ab263aa5b1	[core] code format	2023-05-25 15:02:03 -07:00
tangxifan	8d7429fc2b	[core] adding the new command 'write_mock_fpga_wrapper'	2023-05-25 12:58:12 -07:00
tangxifan	b569d6b603	[core] format	2023-01-07 11:40:17 -08:00
tangxifan	c7a4d25e35	[core] now all the commands can be optionally hidden	2023-01-07 11:36:10 -08:00
tangxifan	401b640852	[core] format	2023-01-06 17:50:47 -08:00
tangxifan	12134f4106	[core] now openfpga verilog commands follow templates	2023-01-06 17:48:00 -08:00