tangxifan
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7503c58fb2
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small fix on SDC generator for SB which do not exist in FPGA
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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d0793d9029
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now disable_sb_output support wildcard
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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facd87dafe
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use wildcard in SDC generation for multiple-instanced-blocks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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1e2226e1c3
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now use explicit port mapping in the verilog testbenches for reference benchmarks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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69306faf22
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add a new include netlist for all the fabric-related netlists
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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87b17fc25f
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add netlist manager data structure
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2020-04-23 18:59:09 -06:00 |
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tangxifan
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bf841b9a8e
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bug fixed in identifying wired LUT
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2020-04-22 17:28:16 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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2e3054f79a
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bug fixed for SDC generation for LUTs
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2020-04-21 14:34:51 -06:00 |
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tangxifan
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68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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3f1fb70d16
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FPGA SDC now constrain max and min delay for primitive modules in grids
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2020-04-21 11:00:28 -06:00 |
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tangxifan
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c2804a4c1f
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bug fix for RC delay computing in SDC generation
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2020-04-20 22:20:00 -06:00 |
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tangxifan
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1a8968cb37
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now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
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2020-04-20 21:12:51 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
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a7d900088b
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now generating simulation ini file will try to create directory first
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2020-04-15 20:53:37 -06:00 |
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tangxifan
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72e8824a87
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bug fixed on removing undriven pins (direct connection between clbs) from cb
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2020-04-15 20:41:15 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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56e0d2a918
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critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
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2020-04-13 12:58:44 -06:00 |
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tangxifan
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e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
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b9dab2baaf
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add exit codes to command execution in shell context
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2020-04-08 16:18:05 -06:00 |
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tangxifan
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1fb37f4c71
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improve directory creator to support same functionality as 'mkdir -p'
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2020-04-08 12:55:09 -06:00 |
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tangxifan
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0b1c8ac139
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bug fixed in identifying the physical interconnect for pb_graph nodes
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2020-04-07 19:46:42 -06:00 |
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tangxifan
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62276f9e28
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minor code format
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2020-04-07 18:43:11 -06:00 |
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tangxifan
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cbcd1d20d4
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fixed memory leakage in pb_pin fixup
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2020-04-07 16:24:04 -06:00 |
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tangxifan
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5a04da2082
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fix memory leakage in openfpga title
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2020-04-07 16:14:41 -06:00 |
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tangxifan
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26d1261c1f
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add test cases using shift registers
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2020-04-07 15:09:10 -06:00 |
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tangxifan
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92a3a444f9
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update VPR7 to support global I/O ports
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2020-04-06 20:44:00 -06:00 |
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tangxifan
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3369d724e9
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bug fixing in Verilog top-level testbench generation
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2020-04-05 17:50:11 -06:00 |
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tangxifan
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decc1dc4b2
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debugged global gp input/output port support
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2020-04-05 17:39:30 -06:00 |
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tangxifan
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bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
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5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
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bc47b3ca94
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update verilog module writer to the global spy ports
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2020-04-05 16:04:13 -06:00 |
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tangxifan
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8b583b7917
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debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
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836f722f20
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start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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tangxifan
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63306ce3a0
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add comments to explain the memory organization in the top-level module
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2020-04-01 11:05:30 -06:00 |
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tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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4bf0a63ae6
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bug fixed for multiple io types defined in FPGA architectures
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2020-03-27 16:32:15 -06:00 |
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tangxifan
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7c9c2451f2
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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tangxifan
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329b0a9cf1
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add options to enable SDC constraints on zero-delay paths
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2020-03-25 15:55:30 -06:00 |
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tangxifan
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4a0128f240
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minor fix on the SDC format
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2020-03-25 14:46:31 -06:00 |
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tangxifan
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c2e5d6b8e2
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add options to dsiable SDC for non-clock global ports
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2020-03-25 14:38:13 -06:00 |
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tangxifan
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787dc8ce83
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added ASCII OpenFPGA logo in shell interface
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2020-03-25 11:16:04 -06:00 |
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tangxifan
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b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
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9e4e12aae9
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fixed echo message in the compression rate of gsb uniquifying
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2020-03-22 16:13:04 -06:00 |