AurelienUoU
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182d49da45
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Update regression test scripts
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2019-06-06 11:47:51 -06:00 |
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AurelienUoU
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a2f6ded2a2
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Add path modification in file changing a keyword into OpenFPGA full path
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2019-06-04 15:21:15 -06:00 |
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AurelienUoU
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eb72cb201c
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Use debug cmake build type to avoid building error
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2019-06-03 15:34:26 -06:00 |
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AurelienUoU
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f51aa41c23
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Correct gcc instantiation
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2019-06-03 14:13:22 -06:00 |
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AurelienUoU
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f4b8c3cf25
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Try another combination cmake/gcc
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2019-06-03 13:45:34 -06:00 |
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AurelienUoU
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ab9834798a
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Test if travis issue is the same as spotted on VM
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2019-06-03 12:01:37 -06:00 |
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AurelienUoU
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8a5ff37262
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Verify cmake version called to build
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2019-06-03 11:16:39 -06:00 |
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AurelienUoU
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737300eb54
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Fix regression test
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2019-05-31 11:00:30 -06:00 |
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AurelienUoU
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0e820d38ea
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Speedup the install on travis
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2019-05-29 16:53:35 -06:00 |
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AurelienUoU
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af01ca4a0d
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Path correction in travis regression test
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2019-05-20 08:53:19 -06:00 |
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AurelienUoU
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17ad905b14
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Update flow and allow netlist generation
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2019-05-17 17:00:38 -06:00 |
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AurelienUoU
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df8bb0db1a
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Add MCNC Benchmarks netlists generation to travis regression test
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2019-05-17 15:22:04 -06:00 |
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AurelienUoU
|
9b28b303b4
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Correction of path error
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2019-05-16 15:05:34 -06:00 |
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AurelienUoU
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f31339bb5c
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Correctly instantiate script variables
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2019-05-16 14:30:16 -06:00 |
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AurelienUoU
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c4ccff4562
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Move Verilog test in another script to avoid false failure
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2019-05-16 09:05:30 -06:00 |
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AurelienUoU
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08f63c06c7
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Debug for Travis
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2019-05-15 16:55:18 -06:00 |
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AurelienUoU
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57d75520a6
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Verilog verification with Travis
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2019-05-15 15:57:05 -06:00 |
tangxifan
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b04c6b8c31
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bug fix on Makefile and travis
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2019-05-03 23:24:08 -06:00 |
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tangxifan
|
c5ef99f6d4
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update travis
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2019-05-03 23:18:31 -06:00 |
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tangxifan
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e2e4a9287d
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keep bug fixing in Makefiles and remove parallism in Make
|
2019-04-10 16:10:19 +08:00 |
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tangxifan
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7c42119481
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Keep bug fixing for travis
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2019-04-10 16:00:03 +08:00 |
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tangxifan
|
f1290ff7b9
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correct travis errors
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2019-04-10 15:29:39 +08:00 |
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tangxifan
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5c46e4aabf
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add missing files for Travis
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2019-04-10 15:24:37 +08:00 |