Commit Graph

7 Commits

Author SHA1 Message Date
tangxifan f70f387f9f minor tuning on ini compilation 2019-11-01 20:51:49 -06:00
tangxifan 3669a47d3b reworked the ini writer 2019-11-01 20:25:01 -06:00
Ganesh Gore a3e9b4aea9 Added mINI/lib - INI Read write to project 2019-09-27 13:58:48 -06:00
tangxifan 2c7d6e3de4 adding port parsers 2019-08-09 17:48:55 -06:00
tangxifan ad8c33e1ba complete the mutators 2019-08-08 11:33:11 -06:00
tangxifan 38962c4607 adding member functions for circuit library 2019-08-07 15:45:27 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00