Commit Graph

9 Commits

Author SHA1 Message Date
tangxifan ddfb0c4afd [core] now mock fpga top supports fpga core wrapper 2023-06-26 15:06:11 -07:00
tangxifan 205881d0e7 [core] fixed the bug when using fpga_core instead of fpga_top 2023-06-25 18:03:15 -07:00
tangxifan 150653287d [core] supporting io naming for verilog testbench generators 2023-06-25 15:29:27 -07:00
tangxifan a9e5e1af89 [core] now fabric netlist include mock wrapper 2023-05-26 18:49:57 -07:00
tangxifan 45e25e4152 [core] hooking up API with command 2023-05-25 19:50:39 -07:00
tangxifan ab263aa5b1 [core] code format 2023-05-25 15:02:03 -07:00
tangxifan 8d7429fc2b [core] adding the new command 'write_mock_fpga_wrapper' 2023-05-25 12:58:12 -07:00
tangxifan 401b640852 [core] format 2023-01-06 17:50:47 -08:00
tangxifan 12134f4106 [core] now openfpga verilog commands follow templates 2023-01-06 17:48:00 -08:00