tangxifan
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f25081eb31
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[test] add a new test to validate ecb when tile modules are used
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2024-05-20 21:10:49 -07:00 |
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tangxifan
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5f6050d404
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[test] add a new test to validate combo: group tile, tile annotation and subtile
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2023-08-18 21:48:40 -07:00 |
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tangxifan
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e82e4f487e
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[test] add a new test to validate io subtile support
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2023-08-18 11:13:34 -07:00 |
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tangxifan
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667c5f8944
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[test] fixed a bug on the testcase
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2023-07-27 22:02:28 -07:00 |
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tangxifan
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952e84fce1
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[test] now heterogeneous testcases for tile modules pass
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2023-07-27 20:30:32 -07:00 |
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tangxifan
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beaa687a20
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[core] fixed bugs on supporting heterogeneous blocks in tile modules
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2023-07-27 20:29:18 -07:00 |
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tangxifan
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65995d7c13
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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tangxifan
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46e58a56cb
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[test] added a new test case to validate clock network when using the tile modules
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2023-07-27 16:39:48 -07:00 |
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tangxifan
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81d699a723
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[test] added a new testcase to validate carry chain connections in tile modules
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2023-07-27 16:18:30 -07:00 |
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tangxifan
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e9f2adf3f9
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[test] add a new testcase to validate carry chain connections when using tile modules
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2023-07-27 16:06:43 -07:00 |
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tangxifan
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1ea8a33d4b
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[test] add a new testcase to validate global tile connections on tile modules
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2023-07-27 15:57:38 -07:00 |
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tangxifan
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a2848940df
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[test] add a new testcase to ease debugging
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2023-07-26 22:32:03 -07:00 |
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tangxifan
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5685fbd5e8
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[test] adding a new test case to validate the tile modules on 4x4 fabric
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2023-07-26 22:17:39 -07:00 |
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tangxifan
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0db4ef62e8
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[test] add a new test for tile-based fabric: using preconfig testbenches
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2023-07-25 15:48:14 -07:00 |
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tangxifan
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82fe63297a
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[test] add a new test for top-left tile grouping
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2023-07-19 11:22:36 -07:00 |
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tangxifan
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8d02a6e600
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[test] now testcases are using proper arch
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2023-05-03 21:47:21 +08:00 |
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tangxifan
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df771cb33a
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[test] add a new testcase for subtile and deploy it to basic regression test
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2023-05-03 15:41:29 +08:00 |
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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tangxifan
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0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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61376a2979
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[Test] Add test cases for various tile organization
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2020-11-04 16:32:52 -07:00 |