tangxifan
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50e201feeb
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[core] now clock routing for programmable clock network works for 1 clock design
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2023-03-07 13:13:25 -08:00 |
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tangxifan
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2ff3ad61ce
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[core] format
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2023-03-06 21:57:44 -08:00 |
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tangxifan
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45107bf14f
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[core] debugging
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2023-03-06 21:48:19 -08:00 |
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tangxifan
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6f2572324e
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[core] developing route clock rr_graph command
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2023-02-28 11:52:38 -08:00 |
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tangxifan
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009d711ba5
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[core] code format
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2023-02-26 22:23:41 -08:00 |
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tangxifan
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87a9146082
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[core] adding rr spatial lookup for clock nodes only
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2023-02-26 22:23:17 -08:00 |
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tangxifan
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7f07a9d031
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[lib] add default seg/switch to clock arch. Fixed syntax
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2023-02-24 19:15:39 -08:00 |
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tangxifan
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ee0459d729
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[core] developing append_clock_rr_graph function
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2023-02-24 17:58:37 -08:00 |
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tangxifan
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aa55c692d7
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[core] starting developing core function for clock rr_graph build-up
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2023-02-23 18:04:07 -08:00 |
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tangxifan
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786b458a27
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[core] adding new command 'append_clock_rr_graph'
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2023-02-23 13:30:18 -08:00 |
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tangxifan
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f00acf1e62
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[code] fixed all the compiler warnings under openfpga/src
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2023-01-31 12:51:52 -08:00 |
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tangxifan
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52e803804d
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[core] add missing file
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2023-01-06 22:37:55 -08:00 |