55be8f491e
fix mux syntax in circuit_model_examples
...
the documentation is inconsistent about using underscores or dashes when describing a mux. It used one-level, but multi_level. Only underscores are valid in openfpga
2023-02-10 10:22:37 -07:00
e660880419
[doc] fixed bugs on small figure sizes shown
2022-12-06 17:20:46 -08:00
0609210b39
[doc] update doc with the new xml syntax
2022-09-08 17:00:16 -07:00
781250f0bb
Fix a small typo to trigger the CI flow.
2022-03-22 16:36:45 -07:00
6ff69d26b9
[Doc] An example to the documentation about the new feature in tile_annotation
2022-03-20 13:12:13 +08:00
123bb70cb3
[Doc] More explanantion on the use of config_enable attribute for circuit ports
2022-02-23 15:53:58 -08:00
57159fc121
[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
2021-10-10 17:46:45 -07:00
40b589dc6d
[Doc] Update documentation about the clock definition for programming clocks in simulation settings
2021-10-06 13:50:33 -07:00
ff339312f6
[Doc] Update documentation about the limitations of multi-region configuration protocols
2021-10-05 11:55:10 -07:00
a01fa7c282
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
2021-10-04 12:09:42 -07:00
b0a97a7052
[Doc] Update doc about WLR usage for QL memory bank
2021-09-27 10:24:04 -07:00
f9bceff33a
[Doc] Update documentation for the flatten BL/WL protocols
2021-09-25 20:44:45 -07:00
d9d959709c
[Doc] Add missing figures
2021-09-20 20:31:53 -07:00
3146d2484f
[Doc] Update documentation on the WLR definition for circuit model
2021-09-20 17:21:33 -07:00
73d21c9730
[Doc] Update doc about how to use the QuickLogic memory bank
2021-09-10 15:30:37 -07:00
9b40e74e25
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
2021-05-24 15:24:50 -06:00
21a18069a1
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
2021-05-24 14:50:55 -06:00
b6b98a75b8
[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
2021-05-24 13:03:40 -06:00
62dc5a3856
[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
2021-04-24 16:02:24 -06:00
19b2641839
Merge branch 'master' into doc_patch
2021-03-15 11:45:32 -06:00
fb7d76545e
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
2021-03-15 11:40:09 -06:00
ff0faeb285
[Doc] Update documentation about the extended bitstream setting
2021-03-10 21:41:59 -07:00
01b9bf2a02
[Doc] Update num_region XML for config protocol
2021-02-18 21:58:30 -07:00
1c4dc9f74b
[Doc] Update documentation about the super LUT feature
2021-02-10 11:49:59 -07:00
9c5368f912
[Doc] Correct bugs in compiling latexpdf
2021-02-07 16:17:54 -07:00
9b5c64f35f
[Doc] Update documentation about disable_packing syntax
2021-02-04 16:41:24 -07:00
d53d3963d4
[Doc] Broken link fix in config protocol documentation
2021-01-26 14:05:11 -07:00
e9dc708d66
[Doc] Group file format documentation into a unified section
2021-01-19 19:44:44 -07:00
c4d3e7c50c
[Doc] Update documentation for the new XML syntax in simulation settings
2021-01-15 12:30:26 -07:00
0c808bec41
[Doc] Add clarification for defining multi-bit global tile ports
2021-01-09 20:00:16 -07:00
2324edc522
[Doc] Update documentation for upgraded tile annotation
2021-01-09 18:55:16 -07:00
226f6b8d6d
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
2021-01-04 18:30:04 -07:00
406edeec89
[Doc] Typo fix
2020-12-04 15:07:02 -07:00
4fe190fa7e
[Doc] Bug fix in LUT circuit model documentation
2020-12-04 14:44:27 -07:00
8350b0f911
[Doc] Update documentation about default value definition in tile annotation
2020-12-02 17:08:34 -07:00
cc0114459a
[Doc] Enrich examples for LUT circuit models
2020-11-26 13:03:12 -07:00
62e804215b
[Doc] Add svg figures for LUT examples
2020-11-26 12:35:39 -07:00
2b9a97729e
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
2020-11-23 15:09:47 -07:00
f6126d1ed6
[Doc] Add illustrative example to diff between global ports definitions
2020-11-12 09:24:39 -07:00
bc43c876b0
[Doc] Update documentation for the rules in global port definition for tile ports
2020-11-11 14:10:11 -07:00
2c269c532a
[Doc] Update doc for the global port definition using physical tile port
2020-11-10 20:48:28 -07:00
056b7c0c79
[Doc] Update documentation about CCFF circuit model examples
2020-11-06 12:22:22 -07:00
849ecc7fc0
[Doc] Add notes for using the is_data_io syntax
2020-11-05 09:30:19 -07:00
9bce2f3818
[Doc] Update documentation for new XML syntax "is_data_io"
2020-11-05 09:28:46 -07:00
7e940980e1
[Doc] Update documentation about configuration regions for frame-based protocol
2020-10-30 21:52:01 -06:00
c2c384e24b
[Doc] update documentation about memory bank definition
2020-10-29 17:04:25 -06:00
ccaa697e5a
[Documentation] Add links to technical features to examples
2020-10-10 22:40:37 -06:00
639d57016b
[Documentation] Update documentation about the multi-region configuration
2020-09-29 15:55:42 -06:00
462886fb5f
[Documentation] Update documentation for the multiple region support on configuration chain
2020-09-29 14:02:03 -06:00
7a2502ddf9
[documentation] add more guidelines about the vpr-openfpga architecture annotation
2020-09-02 22:47:14 -06:00
scott-temple
tangxifan
taoli4rs