tangxifan
|
074811a612
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[Script] Now counter benchmarks should pass on the implicit verilog test case
|
2022-02-15 16:47:14 -08:00 |
|
tangxifan
|
1370be0817
|
[Script] Fixing bugs
|
2022-02-15 16:44:51 -08:00 |
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tangxifan
|
8be0868a3b
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[Test] Update test case which uses counter benchmarks: adding pin constraints
|
2022-02-15 16:29:06 -08:00 |
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tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
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tangxifan
|
fae5e1dfdf
|
[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
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2021-06-25 15:16:37 -06:00 |
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tangxifan
|
d40cf98c48
|
[Test] Update test cases by using default net type in testbench generator
|
2021-06-14 11:47:28 -06:00 |
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tangxifan
|
4e3f589810
|
[Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench'
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2021-06-09 13:53:28 -06:00 |
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tangxifan
|
f9404dc97d
|
[Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench'
|
2021-06-09 11:55:25 -06:00 |
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tangxifan
|
9adf94bfd3
|
[Script] Update all the openshell scripts to deprecate 'write_verilog_testbench'
|
2021-06-09 11:18:52 -06:00 |
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tangxifan
|
b4b6ada06f
|
[Script] Correct bugs in example scripts using default_net_type
|
2021-02-28 16:31:44 -07:00 |
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tangxifan
|
d7eb159726
|
[Script] Add default net type option to example openfpga shell scripts
|
2021-02-28 12:08:30 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |