tangxifan
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3c6fdee8d3
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Merge pull request #1848 from lnis-uofu/dependabot/submodules/yosys-59404f8
Bump yosys from `8e1e2b9` to `59404f8`
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2024-09-30 12:32:13 -07:00 |
dependabot[bot]
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d777c7d29a
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Bump yosys from `8e1e2b9` to `59404f8`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8e1e2b9` to `59404f8`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8e1e2b9a39...59404f8ce5)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2024-09-30 06:07:28 +00:00 |
Lin
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bceb160ab8
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reformat code
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2024-09-29 13:20:49 +08:00 |
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Lin
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7d9a677534
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changed file name
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2024-09-29 13:17:13 +08:00 |
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Lin
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20238c1a2d
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modified testcase
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2024-09-29 12:30:39 +08:00 |
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Lin
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bddf693d7b
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read bin ready
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2024-09-29 12:22:02 +08:00 |
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Lin
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6864159f31
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modified testcases
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2024-09-29 11:20:46 +08:00 |
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Lin
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87ca9f3006
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add three testcases to test bin read and write
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2024-09-29 11:09:01 +08:00 |
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Lin
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08ec3760e4
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mod read bin
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2024-09-29 10:46:50 +08:00 |
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Lin
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ed381692a7
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read bin format mod (with bug)
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2024-09-27 18:41:30 +08:00 |
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Lin
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59f1e4adc9
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add read bin (with bugs)
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2024-09-27 18:28:53 +08:00 |
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Lin
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1d6f9901bb
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renamed file
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2024-09-27 17:23:17 +08:00 |
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Lin
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ef18d04a3a
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write bin function works now
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2024-09-27 17:21:24 +08:00 |
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Lin
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3fcdc10d3a
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write bin function no compile error
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2024-09-27 11:34:57 +08:00 |
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Lin
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0cca4952bc
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write bin format function (with bug)
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2024-09-26 18:01:13 +08:00 |
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Lin
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5174b7a336
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add capnp for unique blocks and add write bin function
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2024-09-26 17:39:52 +08:00 |
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Lin
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faa222f2c1
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create capnp folder
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2024-09-25 18:42:04 +08:00 |
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tangxifan
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4af766930b
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Merge pull request #1846 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-09-24 05:42:21 -07:00 |
github-actions[bot]
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1c70b797f8
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Updated Patch Count
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2024-09-24 09:56:27 +00:00 |
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tangxifan
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5072872a82
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Merge pull request #1845 from lnis-uofu/dependabot/submodules/yosys-8e1e2b9
Bump yosys from `4d581a9` to `8e1e2b9`
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2024-09-24 02:56:06 -07:00 |
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dependabot[bot]
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9b7583ff51
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Bump yosys from `4d581a9` to `8e1e2b9`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `4d581a9` to `8e1e2b9`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](4d581a97d6...8e1e2b9a39)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2024-09-24 06:44:52 +00:00 |
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tangxifan
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ece9fc0eb8
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Merge pull request #1844 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-09-21 23:35:40 -07:00 |
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github-actions[bot]
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1ce23c425f
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Updated Patch Count
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2024-09-22 06:34:46 +00:00 |
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tangxifan
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41cf56e372
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Merge pull request #1843 from lnis-uofu/xt_clkmux
Support intermediate drivers in programmable clock network
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2024-09-21 23:34:25 -07:00 |
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tangxifan
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c52610959c
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[core] code format
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2024-09-21 21:54:37 -07:00 |
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tangxifan
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f009180bbf
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[core] refactor
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2024-09-21 21:53:53 -07:00 |
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tangxifan
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415fd9a8fa
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[core] code format
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2024-09-21 21:39:30 -07:00 |
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tangxifan
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9e461284d0
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[core] standardize API for clock network intermeidate drivers
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2024-09-21 21:38:32 -07:00 |
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tangxifan
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af09120a52
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[doc] update fig
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2024-09-21 13:35:42 -07:00 |
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tangxifan
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26cda624d3
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[doc] add new syntax about clock network
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2024-09-21 13:31:30 -07:00 |
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tangxifan
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4e85a6f414
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[core] code format
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2024-09-20 22:37:05 -07:00 |
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tangxifan
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33a253da3d
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[core] fixed the bug
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2024-09-20 22:20:41 -07:00 |
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tangxifan
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6551ca81e5
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[core] debugging
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2024-09-20 19:48:02 -07:00 |
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tangxifan
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6d3d36626e
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[test] typo
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2024-09-20 19:29:47 -07:00 |
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tangxifan
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ed33b62a60
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[test] add new tests to validate intermediate drivers in clock
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2024-09-20 19:27:40 -07:00 |
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tangxifan
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2bb87ea278
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[core] code format
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2024-09-20 19:23:14 -07:00 |
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tangxifan
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f87e095558
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[core] support intermediate driver in clock routing
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2024-09-20 19:22:39 -07:00 |
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tangxifan
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e8957b6fd8
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[core] enable clock intermediate driver in rrgraph buildup
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2024-09-20 19:07:16 -07:00 |
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tangxifan
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1332d426c7
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[core] code format
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2024-09-20 17:42:53 -07:00 |
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tangxifan
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965ee2190e
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[core] support intermediate driver in clock arch
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2024-09-20 17:42:26 -07:00 |
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tangxifan
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9a9d684f58
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Merge pull request #1842 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-09-19 12:12:56 -07:00 |
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github-actions[bot]
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fcb151d0f4
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Updated Patch Count
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2024-09-19 18:43:09 +00:00 |
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tangxifan
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0c43e99d39
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Merge pull request #1841 from lnis-uofu/xt_mux
Support last stage pass-gate-logic model for MUX circuit model
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2024-09-19 11:42:50 -07:00 |
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tangxifan
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4905e694ab
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[doc] typo
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2024-09-18 21:59:06 -07:00 |
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tangxifan
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8e04d473f2
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[core] code format
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2024-09-18 21:10:31 -07:00 |
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tangxifan
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44a07704ff
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[core] add check codes for last stage pgl model
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2024-09-18 21:10:02 -07:00 |
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tangxifan
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1789ce06c4
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[doc] update new syntax with example
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2024-09-18 17:55:05 -07:00 |
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tangxifan
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f6b645fd25
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[core] code format
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2024-09-18 17:44:55 -07:00 |
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tangxifan
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1673d9b919
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[core] fixed a bug
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2024-09-18 17:43:41 -07:00 |
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tangxifan
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7b4f06ed7d
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[test] validate mux2 at last stage
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2024-09-18 17:40:13 -07:00 |