Merge pull request #1841 from lnis-uofu/xt_mux
Support last stage pass-gate-logic model for MUX circuit model
This commit is contained in:
tangxifan
GitHub
commit
0c43e99d39
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@ -53,6 +53,7 @@ Here, we focus these common syntax and we will detail special syntax in :ref:`ci
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<input_buffer exist="<string>" circuit_model_name="<string>"/>
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<output_buffer exist="<string>" circuit_model_name="<string>"/>
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<pass_gate_logic type="<string>" circuit_model_name="<string>"/>
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<last_stage_pass_gate_logic type="<string>" circuit_model_name="<string>"/>
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<port type="<string>" prefix="<string>" lib_name="<string>" size="<int>" default_val="<int>" circuit_model_name="<string>" mode_select="<bool>" is_global="<bool>" is_set="<bool>" is_reset="<bool>" is_config_enable="<bool>"/>
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<!-- more ports -->
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</circuit_model>
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@ -129,12 +130,16 @@ Input and Output Buffers
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Pass Gate Logic
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^^^^^^^^^^^^^^^
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.. note:: pass-gate logic are used in building multiplexers and LUTs.
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.. option:: <pass_gate_logic circuit_model_name="<string>"/>
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- ``circuit_model_name="<string>"`` Specify the name of the circuit model which is used to implement pass-gate logic, the type of specified circuit model should be ``pass_gate``.
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.. note:: pass-gate logic are used in building multiplexers and LUTs.
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.. option:: <last_stage_pass_gate_logic circuit_model_name="<string>"/>
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- ``circuit_model_name="<string>"`` Specify the name of the circuit model which is used to implement the pass-gate logic at last stage of multiplexer, the type of specified circuit model should be ``pass_gate``. The type of the pass-gate logic circuit model must be a standard cell MUX2!
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.. _circuit_library_circuit_port:
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@ -619,6 +619,14 @@ This example shows:
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Standard Cell Multiplexer
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`````````````````````````
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.. _fig_stdcellmux:
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.. figure:: ./figures/stdcellmux.png
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:width: 100%
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:alt: Examples of MUX built with standard cells
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An example of a multiplexer built with standard cells: (a) all the MUX2 are the same; (b) the MUX2 at the last stage is a different one
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.. code-block:: xml
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<circuit_model type="mux" name="mux_stdcell" prefix="mux_stdcell">
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@ -631,12 +639,34 @@ Standard Cell Multiplexer
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<port type="sram" prefix="sram" size="3"/>
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</circuit_model>
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This example shows:
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This example shows (see an illustative example in :numref:`fig_stdcellmux` (a)):
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- A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2``
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- All the inputs will be buffered using the circuit model ``inv1x``
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- All the outputs will be buffered using the circuit model ``tapbuf4``
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- The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate
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Alternatively, user can specify a different standard cell MUX2 at the last stage.
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.. code-block:: xml
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<circuit_model type="mux" name="mux_stdcell" prefix="mux_stdcell">
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<design_technology type="cmos" structure="tree"/>
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<input_buffer exist="on" circuit_model_name="inv1x"/>
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<output_buffer exist="on" circuit_model_name="tapdrive4"/>
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<pass_gate_logic circuit_model_name="MUX2"/>
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<last_stage_pass_gate_logic circuit_model_name="MUX2D2"/>
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<port type="input" prefix="in" size="4"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="3"/>
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</circuit_model>
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This example shows (see an illustative example in :numref:`fig_stdcellmux` (b)):
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- A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2``
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- The last stage A tree-like 4-input CMOS multiplexer built by the standard cell ``MUX2``
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- All the inputs will be buffered using the circuit model ``inv1x``
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- All the outputs will be buffered using the circuit model ``tapbuf4``
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- The multiplexer will have 4 inputs and 3 SRAMs to control which datapath to propagate
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.. _circuit_model_mux_multilevel_example:
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Multi-level Multiplexer
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Binary file not shown.
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After Width: | Height: | Size: 11 KiB |
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@ -800,6 +800,60 @@ static size_t check_io_circuit_model(const CircuitLibrary& circuit_lib) {
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return num_err;
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}
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/************************************************************************
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* Check the last stage pass gate logic model is the same type as default
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***********************************************************************/
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static size_t check_pass_gate_circuit_model_consistency(
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const CircuitLibrary& circuit_lib) {
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size_t num_err = 0;
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for (const CircuitModelId& mux_model :
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circuit_lib.models_by_type(CIRCUIT_MODEL_MUX)) {
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CircuitModelId pgl_model = circuit_lib.pass_gate_logic_model(mux_model);
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CircuitModelId last_stage_pgl_model =
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circuit_lib.last_stage_pass_gate_logic_model(mux_model);
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if (!circuit_lib.valid_model_id(pgl_model)) {
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VTR_LOGF_ERROR(
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__FILE__, __LINE__,
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"The pass-gate logic circuit model '%s' of '%s' is not valid!\n",
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circuit_lib.pass_gate_logic_model_name(mux_model).c_str(),
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circuit_lib.model_name(mux_model).c_str());
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num_err++;
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}
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if (!circuit_lib.valid_model_id(last_stage_pgl_model)) {
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VTR_LOGF_ERROR(
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__FILE__, __LINE__,
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"The last stage pass-gate logic circuit model '%s' of '%s' is not "
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"valid!\n",
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circuit_lib.last_stage_pass_gate_logic_model_name(mux_model).c_str(),
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circuit_lib.model_name(mux_model).c_str());
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num_err++;
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}
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if (circuit_lib.model_type(pgl_model) !=
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circuit_lib.model_type(last_stage_pgl_model)) {
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VTR_LOGF_ERROR(
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__FILE__, __LINE__,
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"The last stage pass-gate logic circuit model '%s' of '%s' should be "
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"the same type as its regular pass-gate logic model '%s'!\n",
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circuit_lib.model_name(last_stage_pgl_model).c_str(),
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circuit_lib.model_name(mux_model).c_str(),
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circuit_lib.model_name(pgl_model).c_str());
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num_err++;
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}
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if (pgl_model != last_stage_pgl_model &&
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circuit_lib.gate_type(pgl_model) != CIRCUIT_MODEL_GATE_MUX2) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"The last stage pass-gate logic circuit model '%s' of "
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"'%s' should be a MUX2 gate!\n",
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circuit_lib.model_name(last_stage_pgl_model).c_str(),
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circuit_lib.model_name(mux_model).c_str());
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num_err++;
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}
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}
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return num_err;
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}
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/************************************************************************
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* Check points to make sure we have a valid circuit library
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* Detailed checkpoints:
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@ -920,6 +974,9 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
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/* 11. Check power-gated inverter/buffer models */
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num_err += check_power_gated_circuit_models(circuit_lib);
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/* 12. Check pass-gate logic model consistency */
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num_err += check_pass_gate_circuit_model_consistency(circuit_lib);
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/* If we have any errors, exit */
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if (0 < num_err) {
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@ -259,6 +259,28 @@ CircuitModelId CircuitLibrary::pass_gate_logic_model(
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return pgl_model_id;
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}
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/* Find the id of pass-gate circuit model
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* Two cases to be considered:
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* 1. this is a pass-gate circuit model, just find the data and return
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* 2. this circuit model includes a pass-gate, find the link to pass-gate
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* circuit model and go recursively
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*/
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CircuitModelId CircuitLibrary::last_stage_pass_gate_logic_model(
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const CircuitModelId& model_id) const {
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/* validate the model_id */
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VTR_ASSERT(valid_model_id(model_id));
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/* Return the data if this is a pass-gate circuit model */
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if (CIRCUIT_MODEL_PASSGATE == model_type(model_id)) {
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return model_ids_[model_id];
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}
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/* Otherwise, we need to make sure this circuit model contains a pass-gate */
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CircuitModelId pgl_model_id = last_stage_pass_gate_logic_model_ids_[model_id];
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VTR_ASSERT(CircuitModelId::INVALID() != pgl_model_id);
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return pgl_model_id;
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}
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/* Find the name of pass-gate circuit model
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* Two cases to be considered:
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* 1. this is a pass-gate circuit model, just find the data and return
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@ -279,6 +301,26 @@ std::string CircuitLibrary::pass_gate_logic_model_name(
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return pass_gate_logic_model_names_[model_id];
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}
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/* Find the name of pass-gate circuit model
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* Two cases to be considered:
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* 1. this is a pass-gate circuit model, just find the data and return
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* 2. this circuit model includes a pass-gate, find the link to pass-gate
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* circuit model and go recursively
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*/
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std::string CircuitLibrary::last_stage_pass_gate_logic_model_name(
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const CircuitModelId& model_id) const {
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/* validate the model_id */
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VTR_ASSERT(valid_model_id(model_id));
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/* Return the data if this is a pass-gate circuit model */
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if (CIRCUIT_MODEL_PASSGATE == model_type(model_id)) {
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return model_names_[model_id];
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}
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/* Otherwise, we need to make sure this circuit model contains a pass-gate */
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return last_stage_pass_gate_logic_model_names_[model_id];
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}
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/* Return the type of pass gate logic module, only applicable to circuit model
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* whose type is pass-gate logic */
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enum e_circuit_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(
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@ -1262,6 +1304,8 @@ CircuitModelId CircuitLibrary::add_model(
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/* Pass-gate-related parameters */
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pass_gate_logic_model_names_.emplace_back();
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pass_gate_logic_model_ids_.emplace_back(CircuitModelId::INVALID());
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last_stage_pass_gate_logic_model_names_.emplace_back();
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last_stage_pass_gate_logic_model_ids_.emplace_back(CircuitModelId::INVALID());
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/* Delay information */
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delay_types_.emplace_back();
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@ -1485,6 +1529,15 @@ void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id,
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return;
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}
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/* Set pass-gate logic information of a circuit model */
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void CircuitLibrary::set_model_last_stage_pass_gate_logic(
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const CircuitModelId& model_id, const std::string& model_name) {
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/* validate the model_id */
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VTR_ASSERT(valid_model_id(model_id));
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last_stage_pass_gate_logic_model_names_[model_id] = model_name;
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return;
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}
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/* Add a port to a circuit model */
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CircuitPortId CircuitLibrary::add_model_port(
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const CircuitModelId& model_id,
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@ -2174,6 +2227,12 @@ void CircuitLibrary::link_pass_gate_logic_model(
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}
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pass_gate_logic_model_ids_[model_id] =
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model(pass_gate_logic_model_names_[model_id]);
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/* Get the circuit model id by name, skip those with empty names*/
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if (true == last_stage_pass_gate_logic_model_names_[model_id].empty()) {
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return;
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}
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last_stage_pass_gate_logic_model_ids_[model_id] =
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model(last_stage_pass_gate_logic_model_names_[model_id]);
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return;
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}
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@ -272,7 +272,11 @@ class CircuitLibrary {
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const CircuitModelId& model_id) const;
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/* Pass-gate-logic information */
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CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const;
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CircuitModelId last_stage_pass_gate_logic_model(
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const CircuitModelId& model_id) const;
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std::string pass_gate_logic_model_name(const CircuitModelId& model_id) const;
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std::string last_stage_pass_gate_logic_model_name(
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const CircuitModelId& model_id) const;
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enum e_circuit_model_pass_gate_logic_type pass_gate_logic_type(
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const CircuitModelId& model_id) const;
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float pass_gate_logic_pmos_size(const CircuitModelId& model_id) const;
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@ -448,6 +452,8 @@ class CircuitLibrary {
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/* Pass-gate-related parameters */
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void set_model_pass_gate_logic(const CircuitModelId& model_id,
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const std::string& model_name);
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void set_model_last_stage_pass_gate_logic(const CircuitModelId& model_id,
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const std::string& model_name);
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/* Port information */
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CircuitPortId add_model_port(const CircuitModelId& model_id,
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const enum e_circuit_model_port_type& port_type);
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@ -664,6 +670,10 @@ class CircuitLibrary {
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/* Pass-gate-related parameters */
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vtr::vector<CircuitModelId, std::string> pass_gate_logic_model_names_;
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vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_model_ids_;
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vtr::vector<CircuitModelId, std::string>
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last_stage_pass_gate_logic_model_names_;
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vtr::vector<CircuitModelId, CircuitModelId>
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last_stage_pass_gate_logic_model_ids_;
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/* Port information */
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vtr::vector<CircuitPortId, CircuitPortId> port_ids_;
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@ -832,6 +832,25 @@ static void read_xml_circuit_model(pugi::xml_node& xml_model,
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circuit_lib.set_model_pass_gate_logic(
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model, get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data)
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.as_string());
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/* Last stage pass gate is optional */
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size_t num_last_stage_pgl =
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count_children(xml_model, "last_stage_pass_gate_logic", loc_data,
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pugiutil::ReqOpt::OPTIONAL);
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if (0 < num_last_stage_pgl) {
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auto xml_last_stage_pass_gate_logic =
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get_single_child(xml_model, "last_stage_pass_gate_logic", loc_data);
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circuit_lib.set_model_last_stage_pass_gate_logic(
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model, get_attribute(xml_last_stage_pass_gate_logic,
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"circuit_model_name", loc_data)
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.as_string());
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} else {
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/* By default, assume the last stage circuit model is the same as others
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*/
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circuit_lib.set_model_last_stage_pass_gate_logic(
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model,
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get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data)
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.as_string());
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}
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}
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/* Parse all the ports belonging to this circuit model
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@ -593,6 +593,15 @@ static void write_xml_circuit_model(std::fstream& fp, const char* fname,
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circuit_lib.model_name(circuit_lib.pass_gate_logic_model(model)).c_str());
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fp << "/>"
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<< "\n";
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fp << "\t\t\t"
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<< "<last_stage_pass_gate_logic";
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write_xml_attribute(
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fp, "circuit_model_name",
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circuit_lib
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.model_name(circuit_lib.last_stage_pass_gate_logic_model(model))
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.c_str());
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fp << "/>"
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<< "\n";
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}
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/* Write the ports of circuit model */
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@ -496,6 +496,71 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
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module_manager.module_port(std_cell_module_id, std_cell_module_output);
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VTR_ASSERT(1 == std_cell_module_output_port.get_width());
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/* Find module information of the standard cell MUX2 */
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CircuitModelId last_stage_std_cell_model =
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circuit_lib.last_stage_pass_gate_logic_model(mux_model);
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std::string last_stage_std_cell_module_name =
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circuit_lib.model_name(last_stage_std_cell_model);
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/* Get the moduleId for the submodule */
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ModuleId last_stage_std_cell_module_id =
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module_manager.find_module(last_stage_std_cell_module_name);
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/* We must have one */
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VTR_ASSERT(ModuleId::INVALID() != last_stage_std_cell_module_id);
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/* Find the input ports and output ports of the standard cell */
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std::vector<CircuitPortId> last_stage_std_cell_input_ports =
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circuit_lib.model_ports_by_type(last_stage_std_cell_model,
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CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> last_stage_std_cell_output_ports =
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circuit_lib.model_ports_by_type(last_stage_std_cell_model,
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CIRCUIT_MODEL_PORT_OUTPUT, true);
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/* Quick check the requirements on port map */
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VTR_ASSERT(3 == last_stage_std_cell_input_ports.size());
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VTR_ASSERT(1 == last_stage_std_cell_output_ports.size());
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/* Find the module ports of the standard cell MUX2 module */
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std::vector<ModulePortId> last_stage_std_cell_module_inputs;
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std::vector<BasicPort> last_stage_std_cell_module_input_ports;
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/* Input 0 port is the first data path input of the tgate, whose size must be
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* 1 ! */
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for (size_t port_id = 0; port_id < 2; ++port_id) {
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last_stage_std_cell_module_inputs.push_back(module_manager.find_module_port(
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last_stage_std_cell_module_id,
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circuit_lib.port_prefix(last_stage_std_cell_input_ports[port_id])));
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VTR_ASSERT(true == module_manager.valid_module_port_id(
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last_stage_std_cell_module_id,
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last_stage_std_cell_module_inputs[port_id]));
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last_stage_std_cell_module_input_ports.push_back(
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module_manager.module_port(last_stage_std_cell_module_id,
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last_stage_std_cell_module_inputs[port_id]));
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VTR_ASSERT(1 ==
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last_stage_std_cell_module_input_ports[port_id].get_width());
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}
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/* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */
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ModulePortId last_stage_std_cell_module_mem = module_manager.find_module_port(
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last_stage_std_cell_module_id,
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circuit_lib.port_prefix(last_stage_std_cell_input_ports[2]));
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VTR_ASSERT(true ==
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module_manager.valid_module_port_id(
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last_stage_std_cell_module_id, last_stage_std_cell_module_mem));
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BasicPort last_stage_std_cell_module_mem_port = module_manager.module_port(
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last_stage_std_cell_module_id, last_stage_std_cell_module_mem);
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VTR_ASSERT(1 == last_stage_std_cell_module_mem_port.get_width());
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||||
|
||||
/* Output port is the data path output of the standard cell MUX2, whose size
|
||||
* must be 1 ! */
|
||||
ModulePortId last_stage_std_cell_module_output =
|
||||
module_manager.find_module_port(
|
||||
last_stage_std_cell_module_id,
|
||||
circuit_lib.port_prefix(last_stage_std_cell_output_ports[0]));
|
||||
VTR_ASSERT(true == module_manager.valid_module_port_id(
|
||||
last_stage_std_cell_module_id,
|
||||
last_stage_std_cell_module_output));
|
||||
BasicPort last_stage_std_cell_module_output_port = module_manager.module_port(
|
||||
last_stage_std_cell_module_id, last_stage_std_cell_module_output);
|
||||
VTR_ASSERT(1 == last_stage_std_cell_module_output_port.get_width());
|
||||
|
||||
/* Cache Net ids for each level of the multiplexer */
|
||||
std::vector<std::vector<ModuleNetId>> module_nets_by_level;
|
||||
module_nets_by_level.resize(mux_graph.num_node_levels());
|
||||
|
|
@ -518,11 +583,16 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
|
|||
/* To match the standard cell MUX2: We should have only 2 input_nodes */
|
||||
VTR_ASSERT(2 == branch_size);
|
||||
|
||||
/* Last stage MUX model may have a different name */
|
||||
ModuleId curr_stage_std_cell_module_id = std_cell_module_id;
|
||||
if (true == mux_graph.is_node_output(node)) {
|
||||
curr_stage_std_cell_module_id = last_stage_std_cell_module_id;
|
||||
}
|
||||
/* Find the instance id */
|
||||
size_t std_cell_instance_id =
|
||||
module_manager.num_instance(mux_module, std_cell_module_id);
|
||||
module_manager.num_instance(mux_module, curr_stage_std_cell_module_id);
|
||||
/* Add the module to mux_module */
|
||||
module_manager.add_child_module(mux_module, std_cell_module_id);
|
||||
module_manager.add_child_module(mux_module, curr_stage_std_cell_module_id);
|
||||
|
||||
/* Get the node level and index in the current level */
|
||||
size_t output_node_level = mux_graph.node_level(node);
|
||||
|
|
@ -530,9 +600,9 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
|
|||
/* Set a name for the instance */
|
||||
std::string std_cell_instance_name = generate_mux_branch_instance_name(
|
||||
output_node_level, output_node_index_at_level, false);
|
||||
module_manager.set_child_instance_name(mux_module, std_cell_module_id,
|
||||
std_cell_instance_id,
|
||||
std_cell_instance_name);
|
||||
module_manager.set_child_instance_name(
|
||||
mux_module, curr_stage_std_cell_module_id, std_cell_instance_id,
|
||||
std_cell_instance_name);
|
||||
|
||||
/* Add module nets to wire to next stage modules */
|
||||
ModuleNetId branch_net;
|
||||
|
|
@ -540,13 +610,18 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
|
|||
/* This is an output node, we should use existing output nets */
|
||||
MuxOutputId output_id = mux_graph.output_id(node);
|
||||
branch_net = mux_module_output_nets[output_id];
|
||||
module_manager.add_module_net_source(
|
||||
mux_module, branch_net, curr_stage_std_cell_module_id,
|
||||
std_cell_instance_id, last_stage_std_cell_module_output,
|
||||
last_stage_std_cell_module_output_port.get_lsb());
|
||||
} else {
|
||||
VTR_ASSERT(false == mux_graph.is_node_output(node));
|
||||
branch_net = module_manager.create_module_net(mux_module);
|
||||
module_manager.add_module_net_source(
|
||||
mux_module, branch_net, curr_stage_std_cell_module_id,
|
||||
std_cell_instance_id, std_cell_module_output,
|
||||
std_cell_module_output_port.get_lsb());
|
||||
}
|
||||
module_manager.add_module_net_source(
|
||||
mux_module, branch_net, std_cell_module_id, std_cell_instance_id,
|
||||
std_cell_module_output, std_cell_module_output_port.get_lsb());
|
||||
|
||||
/* Record the module net id in the cache */
|
||||
module_nets_by_level[output_node_level][output_node_index_at_level] =
|
||||
|
|
@ -567,10 +642,17 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
|
|||
* Note that standard cell MUX2 only needs mem but NOT mem_inv
|
||||
*/
|
||||
for (const MuxMemId& mem : mems) {
|
||||
module_manager.add_module_net_sink(
|
||||
mux_module, mux_module_mem_nets[mem], std_cell_module_id,
|
||||
std_cell_instance_id, std_cell_module_mem,
|
||||
std_cell_module_mem_port.get_lsb());
|
||||
if (true == mux_graph.is_node_output(node)) {
|
||||
module_manager.add_module_net_sink(
|
||||
mux_module, mux_module_mem_nets[mem], last_stage_std_cell_module_id,
|
||||
std_cell_instance_id, last_stage_std_cell_module_mem,
|
||||
last_stage_std_cell_module_mem_port.get_lsb());
|
||||
} else {
|
||||
module_manager.add_module_net_sink(
|
||||
mux_module, mux_module_mem_nets[mem], std_cell_module_id,
|
||||
std_cell_instance_id, std_cell_module_mem,
|
||||
std_cell_module_mem_port.get_lsb());
|
||||
}
|
||||
}
|
||||
|
||||
/* Wire the branch module inputs to the nets in previous stage */
|
||||
|
|
@ -602,8 +684,15 @@ static void build_cmos_mux_module_mux2_multiplexing_structure(
|
|||
mux_module, mux_module_input_nets[input_id], std_cell_module_id,
|
||||
std_cell_instance_id, std_cell_module_inputs[node_id],
|
||||
std_cell_module_input_ports[node_id].get_lsb());
|
||||
} else if (true == mux_graph.is_node_output(node)) {
|
||||
/* Find the input port of standard cell */
|
||||
module_manager.add_module_net_sink(
|
||||
mux_module,
|
||||
module_nets_by_level[input_node_level][input_node_index_at_level],
|
||||
last_stage_std_cell_module_id, std_cell_instance_id,
|
||||
last_stage_std_cell_module_inputs[node_id],
|
||||
last_stage_std_cell_module_input_ports[node_id].get_lsb());
|
||||
} else {
|
||||
VTR_ASSERT(false == mux_graph.is_node_input(input_nodes[node_id]));
|
||||
/* Find the input port of standard cell */
|
||||
module_manager.add_module_net_sink(
|
||||
mux_module,
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
|
|||
- registerable\_io: If I/Os are registerable (can be either combinational or sequential)
|
||||
- IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os)
|
||||
- stdcell: If circuit designs are built with standard cells only
|
||||
- stdcell_laststage: If circuit designs are built with standard cells only. And the last stage uses a different standard cell
|
||||
- tree\_mux: If routing multiplexers are built with a tree-like structure
|
||||
- localClkGen: The clock signal of CLB can be generated by internal programmable resources
|
||||
- <feature_size>: The technology node which the delay numbers are extracted from.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,236 @@
|
|||
<?xml version="1.0"?>
|
||||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k6_N10_40nm.xml
|
||||
- General purpose logic block
|
||||
- K = 6, N = 8, I = 40
|
||||
- Single mode
|
||||
- Routing architecture
|
||||
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<!-- Define a circuit model for the standard cell MUX2
|
||||
OpenFPGA requires the following truth table for the MUX2
|
||||
When the select signal sel is enabled, the first input, i.e., in0
|
||||
will be propagated to the output, i.e., out
|
||||
If your standard cell provider does not offer the exact truth table,
|
||||
you can simply swap the inputs as shown in the example below
|
||||
-->
|
||||
<circuit_model type="gate" name="MUX2" prefix="MUX2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mux2.v">
|
||||
<design_technology type="cmos" topology="MUX2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in0" lib_name="B" size="1"/>
|
||||
<port type="input" prefix="in1" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="sel" lib_name="S0" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="MUX2D2" prefix="MUX2D2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mux2.v">
|
||||
<design_technology type="cmos" topology="MUX2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in0" lib_name="BB" size="1"/>
|
||||
<port type="input" prefix="in1" lib_name="AA" size="1"/>
|
||||
<port type="input" prefix="sel" lib_name="SS0" size="1"/>
|
||||
<port type="output" prefix="out" lib_name="YY" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
|
||||
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
|
||||
<!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||
<last_stage_pass_gate_logic circuit_model_name="MUX2D2"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||
<last_stage_pass_gate_logic circuit_model_name="MUX2D2"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||
<pass_gate_logic circuit_model_name="MUX2"/>
|
||||
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="64"/>
|
||||
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFRQ" prefix="DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFRQ"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_tree"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:4]"/>
|
||||
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
|
||||
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:5]"/>
|
||||
<port name="out" physical_mode_port="lut6_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -54,6 +54,55 @@ module MUX2(
|
|||
|
||||
endmodule
|
||||
|
||||
module MUX2D2(
|
||||
// iVerilog is buggy on the 'input A' declaration when deposit initial
|
||||
// values
|
||||
input [0:0] AA, // Data input 0
|
||||
input [0:0] BB, // Data input 1
|
||||
input [0:0] SS0, // Select port
|
||||
output [0:0] YY // Data output
|
||||
);
|
||||
|
||||
assign YY = SS0 ? BB : AA;
|
||||
|
||||
// Note:
|
||||
// MUX2 appears will appear in LUTs, routing multiplexers,
|
||||
// being a component in combinational loops
|
||||
// To help convergence in simulation
|
||||
// i.e., to avoid the X (undetermined) signals,
|
||||
// the following timing constraints and signal initialization
|
||||
// has to be added!
|
||||
|
||||
`ifdef ENABLE_TIMING
|
||||
// ------ BEGIN Pin-to-pin Timing constraints -----
|
||||
specify
|
||||
(AA => YY) = (0.001, 0.001);
|
||||
(BB => YY) = (0.001, 0.001);
|
||||
(SS0 => YY) = (0.001, 0.001);
|
||||
endspecify
|
||||
// ------ END Pin-to-pin Timing constraints -----
|
||||
`endif
|
||||
|
||||
`ifdef ENABLE_SIGNAL_INITIALIZATION
|
||||
// ------ BEGIN driver initialization -----
|
||||
initial begin
|
||||
`ifdef ENABLE_FORMAL_VERIFICATION
|
||||
$deposit(AA, 1'b0);
|
||||
$deposit(BB, 1'b0);
|
||||
$deposit(SS0, 1'b0);
|
||||
`else
|
||||
$deposit(AA, $random);
|
||||
$deposit(BB, $random);
|
||||
$deposit(SS0, $random);
|
||||
`endif
|
||||
|
||||
end
|
||||
// ------ END driver initialization -----
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
// Design Name : CARRY_MUX2
|
||||
// File Name : mux2.v
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ run-task fpga_verilog/mux_design/tree_structure $@
|
|||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 $@
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2_last_stage $@
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
|
||||
run-task fpga_verilog/mux_design/local_encoder $@
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_laststage_mux_40nm_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2
|
||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
bench0_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
Loading…
Reference in New Issue