chungshien
dd577e37e0
LUTRAM Support ( #1595 )
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* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
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Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
tangxifan
e20ac5f272
[core] fixed a bug which cause configuration protocols other than ccff failed
2023-04-24 22:46:46 +08:00
tangxifan
18b078d1d5
[core] fixed bugs which cause ci failed
2023-04-24 21:20:07 +08:00
tangxifan
667d9df028
[core] developing testbench generator for ccff v2
2023-04-24 11:36:21 +08:00
tangxifan
ba90f5020b
[core] fixed some bugs which cause netlist generation failed
2023-04-23 16:48:14 +08:00
tangxifan
28b7a12f68
[core] code format
2023-04-23 14:31:35 +08:00
tangxifan
bd511ba515
[core] fixed syntax errors
2023-04-23 14:26:08 +08:00
tangxifan
592765af48
[core] code complete for upgrading netlist generator w.r.t. ccff v2
2023-04-23 13:57:37 +08:00
tangxifan
ea8ae29b53
[core] code format
2023-04-22 15:12:38 +08:00
tangxifan
297a23dee7
[core] fixed syntax errors
2023-04-22 15:09:39 +08:00
tangxifan
5e8e982334
[core] finished developing checkers
2023-04-22 12:44:34 +08:00
tangxifan
6e44f3f5fc
[core] developing ccff_v2 parsers
2023-04-21 17:01:51 +08:00
tangxifan
6d31b319a2
[engine] update source files subject to code formatting rules
2022-10-06 17:08:50 -07:00
tangxifan
e909f4fabe
[lib] rename libopenfpga to libs
2022-08-18 10:27:20 -07:00