289d9d2169
[Bugfix] Honors yosys_tmpl parameter in flow script
2020-12-03 12:24:24 -07:00
59bd7d0f18
[Flow] Changed substitute to safe_sustitute option
2020-11-25 22:09:36 -07:00
fefba0db59
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
2020-11-25 17:29:53 -07:00
1554f583b7
[Flow] Now support explicit variable file for task
2020-11-25 17:22:41 -07:00
521accdc88
Merge pull request #104 from lukefahr/disp_fix
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FLOW: fixed display flag
2020-10-07 09:54:06 -06:00
7b12c28e4f
Merge pull request #102 from lukefahr/blif_bug
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Fixed blif formatting bug
2020-10-06 20:05:02 -06:00
33bbe0ec48
FLOW: fixed display flag
2020-10-06 20:52:28 -04:00
d68427e47b
Fixed blif formatting bug
2020-10-06 20:46:50 -04:00
2d92a1f1af
Edits to enable basic run_fpga_flow.py
2020-10-02 10:18:10 -04:00
747c062f86
BugFix : Flow script accepts extra OpenFPGA arguments
2020-07-27 18:10:43 -06:00
3b6cd885f3
BugFix: Fixed yosys_vpr with openFPGA_Shell
2020-07-22 11:57:04 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
c1b73efa62
Added support for simulation setting file in the task flow
2020-06-10 23:12:30 -06:00
689c4a3e19
BugFix: The filename in the previous commit
2020-04-15 12:44:22 -06:00
7f37bf1441
Added formal verification support to fpga_flow script
2020-04-15 12:24:51 -06:00
f6b3c5854a
Bugfix :
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+ OpenFPGA template variables update
+ Default path for the verilog netlist
2020-04-11 16:45:22 -06:00
8ea272dc2c
Patched the OpenFPGA shell execution bug
2020-04-08 21:28:14 -06:00
583a4d8767
Fixed bug in openfpga_flow script
2020-04-08 12:04:08 -06:00
ea4122a8a4
Updated openfpga_flow and task file to support sheel run
2020-04-06 00:34:36 -06:00
d1d3446568
backedup partial upgrade for fpga_flow script
2020-04-05 11:36:24 -06:00
46bb5ef9d0
Added disp option in openfpga_flow, Default is --nodisp
2020-01-23 10:04:38 -07:00
f0bed1244c
Added blif file folding before VPR run
2020-01-09 16:50:34 -07:00
74b650e9e1
Added fpga_x2p_duplicate_grid_pin option
2019-12-30 12:25:28 -07:00
d1e260f54f
Spice related option added
2019-12-30 12:16:04 -07:00
6bb11918dc
Updated modelsim and collected result
2019-11-16 19:10:04 -07:00
333d10c94c
Added vpr_fpga_verilog_print_simulation_ini option
2019-11-15 14:26:57 -07:00
a880802803
Bug Fix: Corrected read VPR stat filename
2019-11-01 20:51:05 -06:00
595d2d3070
Simple argument shuffle
2019-11-01 18:21:26 -06:00
81180939ca
Bug fix: Missing exit_if_fail flag in fpga_flow script
2019-10-31 09:56:57 -06:00
c034b871bb
Made activity file independent of power option
2019-10-15 16:08:25 -06:00
eaf8ecee86
added _vpr.txt subscript to vpr log files
2019-10-15 16:07:34 -06:00
cd5fd6ce6c
Added explicit checking to VVP execution
2019-09-18 12:14:26 -06:00
169732ccc1
Added verbose option in VVP output
2019-09-17 22:09:37 -06:00
678e3181ba
Made compact_routing_hierarchy options uncond
2019-09-16 21:22:13 -06:00
81b9c5b266
Added flag for VVP exit code
2019-09-14 12:35:47 -06:00
702a7683a8
Ensure strict exit of fpga_flow on error
2019-09-05 10:23:35 -06:00
f4e99c150a
resolve missing variable bug
2019-08-31 21:55:32 -06:00
06c0dbb328
Added docuementation for fpga_flow
2019-08-31 15:19:34 -06:00
02137805c7
Added python version check in flow and task scripts
2019-08-29 22:14:30 -06:00
f558437ae1
Added task for vpr_blif flow
2019-08-25 00:23:39 -06:00
6e7de16ad4
Solved bug in commnad rearrangement
2019-08-22 23:41:25 -06:00
77e2a7bca3
Added execution time logs in flow script
2019-08-22 17:01:38 -06:00
30cbe38d3d
Added Test Modes - Added blif VPR Option
2019-08-22 17:00:59 -06:00
a335a57c6c
Added debug option to commnad line arguments
2019-08-21 11:08:13 -06:00
b7484ef178
Removed traces of old template file
2019-08-20 15:58:19 -06:00
08b0ef3550
Updated validate_command_line_arguments function
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+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
53941eaf5c
Changed yosys output file name
2019-08-19 19:06:46 -06:00
8f8707ff98
Added option to filter results after parsing
2019-08-19 19:04:14 -06:00
7f6c1b3e00
Code re-arrangement
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+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
12c998c12a
Added dockerignore + minor changes in openfpga_flow script
2019-08-17 16:22:52 -06:00
ganeshgore
tangxifan
Andrew Lukefahr