tangxifan
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13cd48c119
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add support on packable/unpackable modes in VPR architecture
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2020-04-06 16:07:49 -06:00 |
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tangxifan
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b09b051249
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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tangxifan
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fc6abc13fd
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add physical tile utils to identify pins that have Fc=0
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2020-03-21 21:02:47 -06:00 |
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tangxifan
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a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
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f90dc5c296
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remove redundant XML codes
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2020-03-12 20:44:07 -06:00 |
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tangxifan
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5be118d695
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tileable rr_graph builder ready to debug
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2020-03-06 16:18:45 -07:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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1b66e837ba
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bug fixing for lb router. Add physical mode to default node expanding settings
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2020-02-21 11:29:00 -07:00 |
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tangxifan
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0b0e00b5f4
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debugging the LbRouter
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2020-02-20 21:56:15 -07:00 |
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tangxifan
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4a05cec037
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add rr_segment binding to circuit model
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2020-02-12 11:21:40 -07:00 |
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tangxifan
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02d6256e95
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pass simple test on pb_type annotation for frac_lut5 architecture
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2020-01-30 21:39:44 -07:00 |
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tangxifan
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01c80b9126
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add sample architecture to be used for Openfpga
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2020-01-27 13:39:13 -07:00 |