tangxifan
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19c0b57df6
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ignore invalid nets when decoding bitstream
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2020-06-16 22:26:36 -06:00 |
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tangxifan
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9d0e002532
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echo path in architecture bitstream database
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2020-06-16 21:29:45 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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3807a940f4
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fixed critical bugs in bitstream generation and now we pass microbenchmarks
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2020-02-28 16:45:50 -07:00 |
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tangxifan
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410dcf6ab6
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debugged LUT bitstream
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2020-02-26 11:42:18 -07:00 |
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tangxifan
|
759758421d
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found the bug in physical pb mode bits and fixed
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2020-02-25 23:45:49 -07:00 |
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tangxifan
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075264e3e3
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debugging LUT bitstream generation
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2020-02-25 23:29:16 -07:00 |
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tangxifan
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2c44c70557
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bring pb interconnection bitstream generation online
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2020-02-25 00:28:06 -07:00 |
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tangxifan
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04c69d30c2
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start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
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2020-02-24 19:38:02 -07:00 |