Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Lalit Sharma
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fe74c42252
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Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure
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2021-11-12 01:46:06 -08:00 |
coolbreeze413
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3fa373f8bc
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add plugins, set yosys install for plugin
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2021-11-04 07:22:09 +05:30 |
tangxifan
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812d8c950e
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[Script] Update quicklogic's script to output correct verilog file name
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2021-03-08 21:39:44 -07:00 |
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tangxifan
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c53c41b7a5
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[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
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2021-03-08 21:09:23 -07:00 |
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Lalit Sharma
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6a1ce01084
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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
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Lalit Sharma
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2b2acae757
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Adding command to generate verilog file out of yosys run
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2021-03-05 04:07:02 -08:00 |
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Lalit Sharma
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817729ac86
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Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
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Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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Lalit Sharma
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0038496d9c
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Replacing -openfpga with -family qlf_k4n8
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2021-02-28 21:08:47 -08:00 |
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Lalit Sharma
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1082d3c677
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Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |