Commit Graph

16 Commits

Author SHA1 Message Date
tangxifan 715765d81b [core] code complete for top testbench generator on ccffv2 upgrades 2023-04-24 13:34:44 +08:00
tangxifan 667d9df028 [core] developing testbench generator for ccff v2 2023-04-24 11:36:21 +08:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan fdd75c4ec8 [FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks 2021-10-05 17:54:07 -07:00
tangxifan 9e5debabe1 [FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks 2021-10-01 16:23:38 -07:00
tangxifan 33972fc0ec [FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers 2021-09-30 21:05:41 -07:00
tangxifan 43c569b612 [FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object 2021-09-30 14:47:21 -07:00
tangxifan 33e9b27cb8 [Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs 2021-09-25 20:22:27 -07:00
tangxifan 386812777c [FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs 2021-09-25 12:49:32 -07:00
tangxifan 8b72447dad [FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs 2021-09-24 18:07:07 -07:00
tangxifan 4b8f5f294a [Tool] Capsulate fabric bitstream organization for configuration chain 2021-04-10 14:28:31 -06:00
tangxifan afa0e751da [Tool] Use alias for complex bitstream data types 2021-04-10 14:12:02 -06:00
tangxifan 5bcd559851 [Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification 2020-10-30 17:29:04 -06:00
tangxifan e988e35f81 [Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches 2020-09-29 12:22:10 -06:00