Szymon Kulis
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c4e033ac9b
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Include limits in argparse.cpp
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2021-11-28 07:57:31 +01:00 |
tangxifan
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1d96974b99
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[Tool] Patch to remove compiler warnings
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2021-02-04 16:54:04 -07:00 |
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tangxifan
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2483154c34
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[Tool] Patch disable_packing XML syntax to be consistent with VPR upstream
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2021-02-04 16:28:32 -07:00 |
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tangxifan
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dd4f83a374
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bug fixing to constant string to display interconnect names
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2020-04-07 18:28:19 -06:00 |
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tangxifan
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13cd48c119
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add support on packable/unpackable modes in VPR architecture
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2020-04-06 16:07:49 -06:00 |
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tangxifan
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610c71671f
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experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
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2020-03-24 16:47:45 -06:00 |
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tangxifan
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708fda9606
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fixed a bug in using tileable routing when directlist is enabled
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2020-03-20 16:38:58 -06:00 |
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tangxifan
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a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
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5be118d695
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tileable rr_graph builder ready to debug
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2020-03-06 16:18:45 -07:00 |
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tangxifan
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2d86a02358
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refactored LUT bitstream generation to use vtr logic
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2020-02-25 12:45:13 -07:00 |
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tangxifan
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5006a4395d
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bring RRGraph object and writer online
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2020-01-31 16:39:40 -07:00 |
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tangxifan
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9269d7106d
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move rr_graph back to vpr because the reader and writer requires too much dependency on the core engine
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2020-01-31 15:42:44 -07:00 |
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tangxifan
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fb0bcd7a48
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create rr_graph library to enforce unit test on the new data structures as well as compare to legacy rr_node
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2020-01-31 12:29:50 -07:00 |
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tangxifan
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75c3507acf
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add verbose output option for openfpga linking architecture
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2020-01-31 11:36:58 -07:00 |
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tangxifan
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8a7a4dc48e
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add physical type annotation for interconnects and inference
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2020-01-28 21:59:10 -07:00 |
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tangxifan
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5ecb771673
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debugging the annotation to physical mode of pb_types
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2020-01-27 17:43:22 -07:00 |
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tangxifan
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a6fbbce33e
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start developing the openfpga arch binding to vpr
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2020-01-27 15:31:12 -07:00 |
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tangxifan
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48ecb6e48b
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immigrate XML parser for circuit_lib to library readarchopenfpga
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2020-01-12 18:11:00 -07:00 |
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tangxifan
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2901a6eec5
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add missing tatum file due to the folder name tags is in the git ignore list!!!
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2020-01-03 23:13:49 -05:00 |
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tangxifan
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60cbcf9104
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add missing tatum
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2020-01-03 22:42:17 -05:00 |
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tangxifan
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7a96f866bb
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remove tatum temporarily
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2020-01-03 22:41:49 -05:00 |
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tangxifan
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f1bafffa87
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add vpr8 libs and core engine for further integration
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2020-01-03 16:14:42 -07:00 |
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tangxifan
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f70f387f9f
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minor tuning on ini compilation
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2019-11-01 20:51:49 -06:00 |
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tangxifan
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3669a47d3b
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
Ganesh Gore
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a3e9b4aea9
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Added mINI/lib - INI Read write to project
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2019-09-27 13:58:48 -06:00 |
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tangxifan
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2c7d6e3de4
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adding port parsers
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2019-08-09 17:48:55 -06:00 |
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tangxifan
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ad8c33e1ba
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complete the mutators
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2019-08-08 11:33:11 -06:00 |
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tangxifan
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38962c4607
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adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |