tangxifan
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13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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1943929353
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add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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98fbcb5410
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add time unit test for SDC generation to CI
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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4083fae41a
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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2fbf9c2cfc
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change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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889bc8dbe8
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add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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889f179ce7
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add local encoder test case
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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98a658a013
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bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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6dd8d347e1
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try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
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2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
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f6cea1e17c
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Added test_mode_low benchmark
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2020-06-11 19:31:01 -06:00 |
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CHARAS SAMY
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3c781b18d3
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Added routing benchmark
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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42cede37fa
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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9bf91bd92a
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start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
ganeshgore
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c31b20dc91
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Added support for simulation setting file in the task flow
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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49edeb119c
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BugFix : Relative path for refrence benchmark fixed
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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890ead91b9
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Fixed modelsim include references
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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90f608baea
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changing task mcnc file for debugging (temporarily now) Will be corrected later
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2020-04-23 18:58:39 -06:00 |
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tangxifan
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417d534121
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fine tune mcnc example script to run Modelsim simulations easily
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2020-04-23 16:15:45 -06:00 |
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tangxifan
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df85175765
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fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
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2020-04-22 21:44:52 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
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726185cd5e
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add test cases using spypad architecture
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2020-04-22 12:56:57 -06:00 |
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tangxifan
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73e9006372
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add arch file with spy pads
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2020-04-22 12:56:09 -06:00 |
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tangxifan
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9fb8971281
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add FPGA arch with spypads to portofilo
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2020-04-22 11:12:28 -06:00 |
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tangxifan
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9761d13eef
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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tangxifan
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489ca75230
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adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
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f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
|
8b03ec900f
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fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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32ed609238
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update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
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tangxifan
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98878f474b
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light change on arch file to accelerate mcnc big20 run
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2020-04-19 12:03:31 -06:00 |
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tangxifan
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cc163081f5
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recover mcnc big20 test configuration
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2020-04-18 21:06:43 -06:00 |
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tangxifan
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2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
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f76a3090c4
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add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
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tangxifan
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95863e996a
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minor update on arch to use auto layout sizing
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2020-04-18 18:43:56 -06:00 |
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tangxifan
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2f3a36ee81
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update timing and rename the arch file
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2020-04-18 18:39:47 -06:00 |
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tangxifan
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7ce34be175
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update sample architecture timing
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2020-04-17 22:06:06 -06:00 |
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tangxifan
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2ea4b8a2a2
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add more flagship architectures
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2020-04-17 19:12:27 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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032ebc29e6
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-04-15 12:53:20 -06:00 |
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tangxifan
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1e742a3676
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add test case on auto-check test benches
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2020-04-15 12:52:52 -06:00 |
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ganeshgore
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689c4a3e19
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BugFix: The filename in the previous commit
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2020-04-15 12:44:22 -06:00 |
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tangxifan
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46fe1e84ce
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Merge branch 'dev' into ganesh_dev
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2020-04-15 12:27:51 -06:00 |
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ganeshgore
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7f37bf1441
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Added formal verification support to fpga_flow script
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2020-04-15 12:24:51 -06:00 |
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tangxifan
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7ba3e27371
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add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
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tangxifan
|
e78643f108
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add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
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tangxifan
|
59ea0a6ad5
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add implicit verilog test case to Travis CI
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2020-04-12 20:00:20 -06:00 |
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tangxifan
|
23aef96d3a
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add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
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tangxifan
|
11e9014542
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add notes about debugging the aib FPGA
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2020-04-12 19:07:53 -06:00 |
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tangxifan
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a614e5aad9
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add long adder chain to Travis CI
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2020-04-12 15:43:19 -06:00 |