AurelienUoU
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8e38aa6019
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Merge with heterogeneous for unfracturable LUT bug fix
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2019-08-14 10:10:27 -06:00 |
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AurelienUoU
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40b7f1cc53
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-29 11:45:23 -06:00 |
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AurelienUoU
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ef600bc63f
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Save workspace
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2019-07-12 15:57:41 -06:00 |
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AurelienUoU
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8366f9e7b7
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Update tutorial
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2019-07-08 16:18:08 -06:00 |
Ganesh Gore
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443a73954f
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Removed all local files
+ Removed local configurations and scripts from previous commit
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2019-07-03 14:26:06 -06:00 |
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Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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Ganesh Gore
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54f6ca2687
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Added lattice benchmark settings
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2019-07-01 11:07:23 -06:00 |
tangxifan
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c54f3905d5
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fixed broken fpga flow
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2019-06-28 13:07:04 -06:00 |
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AurelienUoU
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b4c97f86a3
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Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
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AurelienUoU
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df8bb0db1a
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Add MCNC Benchmarks netlists generation to travis regression test
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2019-05-17 15:22:04 -06:00 |