Lalit Sharma
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1082d3c677
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Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |
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Lalit Sharma
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1e48d4f6dc
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Modifying custom yosys script file name
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2021-02-25 22:21:39 -08:00 |
tangxifan
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19f6b221b1
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[Test] Rework comments on runtime
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2021-02-22 15:25:57 -07:00 |
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tangxifan
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4803b0ce42
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[Test] Add test case for sdc controller
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2021-02-22 15:02:14 -07:00 |
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tangxifan
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2e2b1cb6e7
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[Test] Use hetergenenous FPGA architecture in quicklogic tests
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2021-02-22 13:41:04 -07:00 |
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tangxifan
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bc30f62c5a
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[Test] Add test for sdc controller
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2021-02-22 12:41:53 -07:00 |
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tangxifan
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60dc194d8f
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[Test] Bug fix in the 5clock test case
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2021-02-22 11:46:23 -07:00 |
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tangxifan
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71e0026a50
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[Test] Add new test for 5-clock counter to quicklogic tests
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2021-02-22 11:32:17 -07:00 |
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tangxifan
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bc8aa0ebc6
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[Test] Remove routing test from quicklogic's flow test
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2021-02-22 10:22:47 -07:00 |
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Lalit Sharma
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576e6753f6
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Removing 2 more tests which are variant of and design
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2021-02-19 09:11:19 -08:00 |
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Lalit Sharma
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6de0954ca5
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Uncommenting all benchmarks except 2 that requires multiple clocks
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2021-02-19 08:40:26 -08:00 |
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Lalit Sharma
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69cdc11ea5
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Uncommenting the tests that are running fine
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2021-02-18 04:17:12 -08:00 |
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Lalit Sharma
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44a979288b
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Adding quicklogic tests and updating the corresponding conf file to run them
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2021-02-16 23:08:38 -08:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
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Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
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Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
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2020-12-18 03:18:46 -08:00 |
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Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
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Lalit Sharma
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0ee3efb306
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Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |