tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
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1e47203c7c
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[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
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2020-11-02 18:35:26 -07:00 |
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tangxifan
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6bea712db0
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[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
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tangxifan
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22159531c5
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bug fix in power gating support of FPGA-Verilog
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2020-07-22 20:21:38 -06:00 |
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tangxifan
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f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
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tangxifan
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185e574738
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removed redundant include files in all the verilog netlists except the top one
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2020-04-24 20:21:32 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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60f40a9657
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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tangxifan
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cf34339e96
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adapt essential gates for submodule generation
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2020-02-16 11:57:19 -07:00 |