CHARAS SAMY
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0020fe42bf
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Reverted changes to test_mode_low.
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2020-05-11 12:17:45 -06:00 |
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CHARAS SAMY
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e71b9e9881
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Modified testbenches according to new arch.
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2020-05-11 11:46:03 -06:00 |
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CHARAS SAMY
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a5076ae1b0
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Modified testbenches according to new arch.
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2020-05-11 11:40:21 -06:00 |
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CHARAS SAMY
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b74da1fec1
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Regroupped benchmark with their testbench so it's easier to compile them.
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2020-05-06 16:47:34 -06:00 |
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CHARAS SAMY
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15159a9760
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Adding sva_checker, description files and testbenches implementing it.
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2020-05-06 11:35:09 -06:00 |
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CHARAS SAMY
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e43de0b8ed
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Modified test_mode_low for port to match the one testbench generates.
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2020-05-01 16:12:24 -06:00 |
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CHARAS SAMY
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35fccf2214
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Adding decoder task
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2020-05-01 15:56:05 -06:00 |
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CHARAS SAMY
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85bbed1b1f
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Added decoder benchmark
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2020-05-01 15:53:13 -06:00 |
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CHARAS SAMY
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32d244ba63
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Added test_mode_low benchmark
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2020-05-01 10:55:23 -06:00 |
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CHARAS SAMY
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e93ee59e11
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Added routing benchmark
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2020-05-01 09:55:38 -06:00 |
tangxifan
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1e19de6230
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add a new include netlist for all the fabric-related netlists
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2020-04-28 23:21:14 -06:00 |
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tangxifan
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27489ec084
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deploy the fabric/testbench generation only cases to travis
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2020-04-28 18:24:20 -06:00 |
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tangxifan
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f92e5131ef
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add testcases on generate fabric/testbench only
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2020-04-28 18:22:41 -06:00 |
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tangxifan
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47c82f5e35
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update travis script with example run on MCNC big20
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2020-04-28 18:16:52 -06:00 |
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tangxifan
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493879530b
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start testing mcnc_big20 using OpenFPGA tasks
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2020-04-25 20:18:10 -06:00 |
ganeshgore
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a3103f6afe
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BugFix : Relative path for refrence benchmark fixed
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2020-04-25 20:16:17 -06:00 |
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ganeshgore
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9d1b3d6865
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Fixed modelsim include references
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2020-04-24 21:53:57 -06:00 |
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ganeshgore
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9e46b4eb75
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-24 21:30:51 -06:00 |
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tangxifan
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185e574738
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removed redundant include files in all the verilog netlists except the top one
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2020-04-24 20:21:32 -06:00 |
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ganeshgore
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773790bc2c
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-24 11:00:40 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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87b17fc25f
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add netlist manager data structure
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2020-04-23 18:59:09 -06:00 |
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tangxifan
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90f608baea
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changing task mcnc file for debugging (temporarily now) Will be corrected later
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2020-04-23 18:58:39 -06:00 |
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tangxifan
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417d534121
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fine tune mcnc example script to run Modelsim simulations easily
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2020-04-23 16:15:45 -06:00 |
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ganeshgore
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ca793285ca
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-23 12:18:24 -06:00 |
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tangxifan
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df85175765
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fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
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2020-04-22 21:44:52 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
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0c4904065f
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reduce activity error to warning.
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2020-04-22 17:36:02 -06:00 |
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tangxifan
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bf841b9a8e
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bug fixed in identifying wired LUT
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2020-04-22 17:28:16 -06:00 |
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tangxifan
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341f38025e
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add spypad to regression test
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2020-04-22 14:42:30 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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726185cd5e
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add test cases using spypad architecture
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2020-04-22 12:56:57 -06:00 |
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tangxifan
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73e9006372
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add arch file with spy pads
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2020-04-22 12:56:09 -06:00 |
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tangxifan
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9fb8971281
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add FPGA arch with spypads to portofilo
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2020-04-22 11:12:28 -06:00 |
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tangxifan
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9960625b01
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add example spypad architecture
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2020-04-22 11:10:59 -06:00 |
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Xifan Tang
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52adebacfb
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update doc for file options in openfpga bitstream
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2020-04-21 14:40:53 -06:00 |
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tangxifan
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2e3054f79a
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bug fixed for SDC generation for LUTs
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2020-04-21 14:34:51 -06:00 |
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tangxifan
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68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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3f1fb70d16
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FPGA SDC now constrain max and min delay for primitive modules in grids
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2020-04-21 11:00:28 -06:00 |
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tangxifan
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c2804a4c1f
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bug fix for RC delay computing in SDC generation
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2020-04-20 22:20:00 -06:00 |
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tangxifan
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1a8968cb37
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now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
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2020-04-20 21:12:51 -06:00 |
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tangxifan
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9761d13eef
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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tangxifan
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f06f2d72be
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deploy single mode in regression tests
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2020-04-20 13:16:52 -06:00 |
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tangxifan
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489ca75230
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adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
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f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
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8b03ec900f
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fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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32ed609238
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update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
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tangxifan
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98878f474b
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light change on arch file to accelerate mcnc big20 run
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2020-04-19 12:03:31 -06:00 |