tangxifan
|
d8ab1d9a36
|
Merge pull request #1849 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-09-30 12:37:24 -07:00 |
github-actions[bot]
|
f181ddf2a9
|
Updated Patch Count
|
2024-09-30 19:32:35 +00:00 |
|
tangxifan
|
3c6fdee8d3
|
Merge pull request #1848 from lnis-uofu/dependabot/submodules/yosys-59404f8
Bump yosys from `8e1e2b9` to `59404f8`
|
2024-09-30 12:32:13 -07:00 |
dependabot[bot]
|
d777c7d29a
|
Bump yosys from `8e1e2b9` to `59404f8`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8e1e2b9` to `59404f8`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8e1e2b9a39...59404f8ce5)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-09-30 06:07:28 +00:00 |
Lin
|
bceb160ab8
|
reformat code
|
2024-09-29 13:20:49 +08:00 |
|
Lin
|
7d9a677534
|
changed file name
|
2024-09-29 13:17:13 +08:00 |
|
Lin
|
20238c1a2d
|
modified testcase
|
2024-09-29 12:30:39 +08:00 |
|
Lin
|
bddf693d7b
|
read bin ready
|
2024-09-29 12:22:02 +08:00 |
|
Lin
|
6864159f31
|
modified testcases
|
2024-09-29 11:20:46 +08:00 |
|
Lin
|
87ca9f3006
|
add three testcases to test bin read and write
|
2024-09-29 11:09:01 +08:00 |
|
Lin
|
08ec3760e4
|
mod read bin
|
2024-09-29 10:46:50 +08:00 |
|
Lin
|
ed381692a7
|
read bin format mod (with bug)
|
2024-09-27 18:41:30 +08:00 |
|
Lin
|
59f1e4adc9
|
add read bin (with bugs)
|
2024-09-27 18:28:53 +08:00 |
|
Lin
|
1d6f9901bb
|
renamed file
|
2024-09-27 17:23:17 +08:00 |
|
Lin
|
ef18d04a3a
|
write bin function works now
|
2024-09-27 17:21:24 +08:00 |
|
Lin
|
3fcdc10d3a
|
write bin function no compile error
|
2024-09-27 11:34:57 +08:00 |
|
Lin
|
0cca4952bc
|
write bin format function (with bug)
|
2024-09-26 18:01:13 +08:00 |
|
Lin
|
5174b7a336
|
add capnp for unique blocks and add write bin function
|
2024-09-26 17:39:52 +08:00 |
|
Lin
|
faa222f2c1
|
create capnp folder
|
2024-09-25 18:42:04 +08:00 |
|
tangxifan
|
4af766930b
|
Merge pull request #1846 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-09-24 05:42:21 -07:00 |
|
github-actions[bot]
|
1c70b797f8
|
Updated Patch Count
|
2024-09-24 09:56:27 +00:00 |
|
tangxifan
|
5072872a82
|
Merge pull request #1845 from lnis-uofu/dependabot/submodules/yosys-8e1e2b9
Bump yosys from `4d581a9` to `8e1e2b9`
|
2024-09-24 02:56:06 -07:00 |
|
dependabot[bot]
|
9b7583ff51
|
Bump yosys from `4d581a9` to `8e1e2b9`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `4d581a9` to `8e1e2b9`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](4d581a97d6...8e1e2b9a39)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-09-24 06:44:52 +00:00 |
|
tangxifan
|
ece9fc0eb8
|
Merge pull request #1844 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-09-21 23:35:40 -07:00 |
|
github-actions[bot]
|
1ce23c425f
|
Updated Patch Count
|
2024-09-22 06:34:46 +00:00 |
|
tangxifan
|
41cf56e372
|
Merge pull request #1843 from lnis-uofu/xt_clkmux
Support intermediate drivers in programmable clock network
|
2024-09-21 23:34:25 -07:00 |
|
tangxifan
|
c52610959c
|
[core] code format
|
2024-09-21 21:54:37 -07:00 |
|
tangxifan
|
f009180bbf
|
[core] refactor
|
2024-09-21 21:53:53 -07:00 |
|
tangxifan
|
415fd9a8fa
|
[core] code format
|
2024-09-21 21:39:30 -07:00 |
|
tangxifan
|
9e461284d0
|
[core] standardize API for clock network intermeidate drivers
|
2024-09-21 21:38:32 -07:00 |
|
tangxifan
|
af09120a52
|
[doc] update fig
|
2024-09-21 13:35:42 -07:00 |
|
tangxifan
|
26cda624d3
|
[doc] add new syntax about clock network
|
2024-09-21 13:31:30 -07:00 |
|
tangxifan
|
4e85a6f414
|
[core] code format
|
2024-09-20 22:37:05 -07:00 |
|
tangxifan
|
33a253da3d
|
[core] fixed the bug
|
2024-09-20 22:20:41 -07:00 |
|
tangxifan
|
6551ca81e5
|
[core] debugging
|
2024-09-20 19:48:02 -07:00 |
|
tangxifan
|
6d3d36626e
|
[test] typo
|
2024-09-20 19:29:47 -07:00 |
|
tangxifan
|
ed33b62a60
|
[test] add new tests to validate intermediate drivers in clock
|
2024-09-20 19:27:40 -07:00 |
|
tangxifan
|
2bb87ea278
|
[core] code format
|
2024-09-20 19:23:14 -07:00 |
|
tangxifan
|
f87e095558
|
[core] support intermediate driver in clock routing
|
2024-09-20 19:22:39 -07:00 |
|
tangxifan
|
e8957b6fd8
|
[core] enable clock intermediate driver in rrgraph buildup
|
2024-09-20 19:07:16 -07:00 |
|
tangxifan
|
1332d426c7
|
[core] code format
|
2024-09-20 17:42:53 -07:00 |
|
tangxifan
|
965ee2190e
|
[core] support intermediate driver in clock arch
|
2024-09-20 17:42:26 -07:00 |
|
tangxifan
|
9a9d684f58
|
Merge pull request #1842 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-09-19 12:12:56 -07:00 |
|
github-actions[bot]
|
fcb151d0f4
|
Updated Patch Count
|
2024-09-19 18:43:09 +00:00 |
|
tangxifan
|
0c43e99d39
|
Merge pull request #1841 from lnis-uofu/xt_mux
Support last stage pass-gate-logic model for MUX circuit model
|
2024-09-19 11:42:50 -07:00 |
|
tangxifan
|
4905e694ab
|
[doc] typo
|
2024-09-18 21:59:06 -07:00 |
|
tangxifan
|
8e04d473f2
|
[core] code format
|
2024-09-18 21:10:31 -07:00 |
|
tangxifan
|
44a07704ff
|
[core] add check codes for last stage pgl model
|
2024-09-18 21:10:02 -07:00 |
|
tangxifan
|
1789ce06c4
|
[doc] update new syntax with example
|
2024-09-18 17:55:05 -07:00 |
|
tangxifan
|
f6b645fd25
|
[core] code format
|
2024-09-18 17:44:55 -07:00 |