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[core] fixed some bugs

This commit is contained in:
tangxifan 2023-09-06 22:49:56 -07:00
parent bcb82d43af
commit eaadff3448
2 changed files with 2 additions and 2 deletions
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2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -657,7 +657,7 @@ int print_verilog_preconfig_top_module(
fp, fp,
std::string(circuit_name) + std::string(circuit_name) +
std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX), std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE); options.default_net_type());
/* Close the file stream */ /* Close the file stream */
fp.close(); fp.close();

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2678,7 +2678,7 @@ int print_verilog_full_testbench(
fp, fp,
std::string(circuit_name) + std::string(circuit_name) +
std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX), std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE); options.default_net_type());
/* Close the file stream */ /* Close the file stream */
fp.close(); fp.close();