From eaadff34488df158b3e8d41e1bd9b2ef37c0e319 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 Sep 2023 22:49:56 -0700
Subject: [PATCH] [core] fixed some bugs

---
 openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 2 +-
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 550ba2d63..0fa26c73f 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -657,7 +657,7 @@ int print_verilog_preconfig_top_module(
     fp,
     std::string(circuit_name) +
       std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
-    VERILOG_DEFAULT_NET_TYPE_WIRE);
+    options.default_net_type());
 
   /* Close the file stream */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index f7dd1b997..a0993d079 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -2678,7 +2678,7 @@ int print_verilog_full_testbench(
     fp,
     std::string(circuit_name) +
       std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
-    VERILOG_DEFAULT_NET_TYPE_WIRE);
+    options.default_net_type());
 
   /* Close the file stream */
   fp.close();