diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 550ba2d63..0fa26c73f 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -657,7 +657,7 @@ int print_verilog_preconfig_top_module(
     fp,
     std::string(circuit_name) +
       std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
-    VERILOG_DEFAULT_NET_TYPE_WIRE);
+    options.default_net_type());
 
   /* Close the file stream */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index f7dd1b997..a0993d079 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -2678,7 +2678,7 @@ int print_verilog_full_testbench(
     fp,
     std::string(circuit_name) +
       std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
-    VERILOG_DEFAULT_NET_TYPE_WIRE);
+    options.default_net_type());
 
   /* Close the file stream */
   fp.close();