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[Test] Add native fracturable LUT4 test to CI

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tangxifan 2020-11-25 23:02:18 -07:00
parent 3a708cff21
commit dc5e2c99af
1 changed files with 3 additions and 0 deletions
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3
.github/workflows/fpga_verilog_reg_test.sh vendored
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@ -13,6 +13,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mo
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs