From dc5e2c99af88059771267cfaf803a1f22b34f449 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 25 Nov 2020 23:02:18 -0700 Subject: [PATCH] [Test] Add native fracturable LUT4 test to CI --- .github/workflows/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh index 7fcf75b3e..a866b7bfc 100755 --- a/.github/workflows/fpga_verilog_reg_test.sh +++ b/.github/workflows/fpga_verilog_reg_test.sh @@ -13,6 +13,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mo echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs + echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs