diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh
index 7fcf75b3e..a866b7bfc 100755
--- a/.github/workflows/fpga_verilog_reg_test.sh
+++ b/.github/workflows/fpga_verilog_reg_test.sh
@@ -13,6 +13,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mo
 echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
 
+echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
+
 echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs