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master 5c8a59f447 · Merge pull request #1897 from lnis-uofu/patch_update · Updated 2024-11-13 23:36:24 -06:00

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docker 8037380659 · . · Updated 2020-07-09 10:25:11 -05:00	5976 0	Included	ZIP  TAR.GZ
samy_dev 177bf761a9 · . · Updated 2020-07-09 10:18:19 -05:00	6039 9		ZIP  TAR.GZ
samy 0020fe42bf · Reverted changes to test_mode_low. · Updated 2020-05-11 13:17:45 -05:00	6255 15		ZIP  TAR.GZ
GF12LPP_tapeout 5d12f499f0 · hotfix on undriven pins on the connection blocks · Updated 2020-03-29 17:26:23 -05:00	6390 0	Included	ZIP  TAR.GZ
systemc f52eaef622 · Updated flow script and skipped travis upload on failure test setup. · Updated 2019-11-15 15:35:15 -06:00	6967 0	Included	ZIP  TAR.GZ
heterogeneous 6793c67c8d · refactored pb_type and grid Verilog generation · Updated 2019-10-13 22:07:30 -05:00	7145 0	Included	ZIP  TAR.GZ
explicit_verilog 027272c976 · Faster regression test · Updated 2019-10-05 13:10:55 -05:00	7183 0	Included	ZIP  TAR.GZ
documentation 8a046394f8 · add documentation for multi-mode configurable block support · Updated 2019-07-30 17:47:41 -05:00	7485 0	Included	ZIP  TAR.GZ
fpga_spice 28f54961b2 · Merge branch 'multimode_clb' into fpga_spice · Updated 2019-06-15 16:37:26 -05:00	7722 0	Included	ZIP  TAR.GZ
homogeneous_single_mode e2e4a9287d · keep bug fixing in Makefiles and remove parallism in Make · Updated 2019-04-10 03:10:19 -05:00	7925 0	Included	ZIP  TAR.GZ
iccd-2015 d89b03abbb · keep updating readme · Updated 2018-10-01 18:06:54 -05:00	8101 5		ZIP  TAR.GZ