OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h

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2019-04-26 13:23:47 -05:00
void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* subckt_prefix,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);