2020-04-12 15:54:45 -05:00
|
|
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
|
|
|
|
# Configuration file for running experiments
|
|
|
|
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
|
|
|
|
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
|
|
|
|
# Each job execute fpga_flow script on combination of architecture & benchmark
|
|
|
|
|
# timeout_each_job is timeout for each job
|
|
|
|
|
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
|
|
|
|
|
|
|
|
|
[GENERAL]
|
|
|
|
|
run_engine=openfpga_shell
|
|
|
|
|
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
|
|
|
|
|
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
|
|
|
|
power_analysis = true
|
|
|
|
|
spice_output=false
|
|
|
|
|
verilog_output=true
|
|
|
|
|
timeout_each_job = 20*60
|
|
|
|
|
fpga_flow=vpr_blif
|
|
|
|
|
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
|
|
|
|
|
|
2020-04-12 20:07:53 -05:00
|
|
|
#####################################
|
|
|
|
|
# Debugging status
|
|
|
|
|
# Fail in the following cases
|
|
|
|
|
# - tileable routing is used
|
|
|
|
|
# - vpr routing is used
|
|
|
|
|
# - compressed routing is enabled/disabled
|
|
|
|
|
# - duplicated pin is enabled/disabled
|
|
|
|
|
#
|
|
|
|
|
# Therefore, this could be a bug in the VPR
|
|
|
|
|
####################################
|
|
|
|
|
|
2020-04-12 15:54:45 -05:00
|
|
|
[ARCHITECTURES]
|
|
|
|
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
|
|
|
|
|
|
|
|
|
|
[BENCHMARKS]
|
2020-04-19 13:49:07 -05:00
|
|
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.blif
|
2020-04-12 15:54:45 -05:00
|
|
|
|
|
|
|
|
[SYNTHESIS_PARAM]
|
|
|
|
|
bench0_top = top
|
2020-04-19 13:49:07 -05:00
|
|
|
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.act
|
|
|
|
|
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and/and.v
|
2020-04-12 15:54:45 -05:00
|
|
|
bench0_chan_width = 300
|
|
|
|
|
|
|
|
|
|
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
|
|
|
|
end_flow_with_test=
|
|
|
|
|
vpr_fpga_verilog_formal_verification_top_netlist=
|
