tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support. ... Previously, the wire LUT identification is too naive and does not consider all the cases		2020-04-19 16:42:31 -06:00
..
OpenFPGAShellScripts	add duplicated_grid_pin test case to Travis CI	2020-04-12 20:10:51 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
arch	light change on arch file to accelerate mcnc big20 run	2020-04-19 12:03:31 -06:00
benchmarks	update micro benchmark set and regression tests using them	2020-04-19 12:49:07 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Updated openfpga_flow and task file to support sheel run	2020-04-06 00:34:36 -06:00
openfpga_arch	add mcnc big20 test cases and start debugging	2020-04-18 19:25:16 -06:00
scripts	BugFix: The filename in the previous commit	2020-04-15 12:44:22 -06:00
tasks	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00