OpenFPGA/openfpga_flow/misc/qlf_yosys.ys

# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}

synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}

write_verilog -noattr -nohex ${OUTPUT_VERILOG}