OpenFPGA/openfpga_flow/misc/qlf_yosys.ys

# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}

synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}

write_verilog -noattr -nohex ${TOP_MODULE}.v
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00			`# Yosys synthesis script for ${TOP_MODULE}`
			`# Read verilog files`
			`${READ_VERILOG_FILE}`

Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-02 00:31:15 -06:00			`synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}`
Adding a testcase to run yosys quicklogic flow 2020-12-10 04:41:43 -06:00
Adding command to generate verilog file out of yosys run 2021-03-05 06:05:19 -06:00			`write_verilog -noattr -nohex ${TOP_MODULE}.v`