2020-02-12 20:45:14 -06:00
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/********************************************************************
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* This file includes all the reserved words that are used in
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* naming module, blocks, instances and cells in FPGA X2P support,
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* including:
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* Verilog generation, SPICE generation and bitstream generation
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*******************************************************************/
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#ifndef OPENFPGA_RESERVED_WORDS_H
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#define OPENFPGA_RESERVED_WORDS_H
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2020-02-12 21:25:05 -06:00
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/* begin namespace openfpga */
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namespace openfpga {
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2020-06-20 19:25:17 -05:00
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/* Top-level module name */
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constexpr char* FPGA_TOP_MODULE_NAME = "fpga_top";
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constexpr char* CONFIGURABLE_MEMORY_DATA_OUT_NAME = "mem_out";
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2020-02-13 16:27:16 -06:00
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/* IO PORT */
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/* Prefix of global input, output and inout ports of FPGA fabric */
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constexpr char* GIO_INOUT_PREFIX = "gfpga_pad_";
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2020-02-12 21:25:05 -06:00
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2020-02-12 20:45:14 -06:00
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/* Grid naming constant strings */
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constexpr char* GRID_MODULE_NAME_PREFIX = "grid_";
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2020-02-13 16:27:16 -06:00
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constexpr char* LOGICAL_MODULE_NAME_PREFIX = "logical_tile_";
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2020-02-12 20:45:14 -06:00
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/* Memory naming constant strings */
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constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_";
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constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
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constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
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constexpr char* MEMORY_MODULE_POSTFIX = "_mem";
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2020-05-29 21:55:45 -05:00
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constexpr char* MEMORY_BL_PORT_NAME = "bl";
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constexpr char* MEMORY_WL_PORT_NAME = "wl";
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2020-02-12 20:45:14 -06:00
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/* Multiplexer naming constant strings */
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constexpr char* MUX_BASIS_MODULE_POSTFIX = "_basis";
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constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
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constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
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constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
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2020-05-25 23:15:16 -05:00
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/* Decoder naming constant strings */
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constexpr char* DECODER_ENABLE_PORT_NAME = "enable";
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constexpr char* DECODER_ADDRESS_PORT_NAME = "address";
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2020-05-26 19:55:55 -05:00
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constexpr char* DECODER_DATA_IN_PORT_NAME = "data_in";
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constexpr char* DECODER_DATA_OUT_PORT_NAME = "data_out";
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constexpr char* DECODER_DATA_OUT_INV_PORT_NAME = "data_out_inv";
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2020-05-30 16:49:15 -05:00
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constexpr char* DECODER_BL_ADDRESS_PORT_NAME = "bl_address";
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constexpr char* DECODER_WL_ADDRESS_PORT_NAME = "wl_address";
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2020-05-25 23:15:16 -05:00
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2020-05-17 20:45:27 -05:00
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/* Inverted port naming */
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constexpr char* INV_PORT_POSTFIX = "_inv";
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2020-02-12 20:45:14 -06:00
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/* Bitstream file strings */
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constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
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2020-07-05 12:39:46 -05:00
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constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
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constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
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constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
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2020-02-12 21:25:05 -06:00
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} /* end namespace openfpga */
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2020-02-12 20:45:14 -06:00
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#endif
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