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OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h

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refactoring Verilog generation for routing channels
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/***********************************************
* Header file for verilog_routing.cpp
**********************************************/
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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#ifndef VERILOG_ROUTING_H
#define VERILOG_ROUTING_H
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/* Include other header files which are dependency on the function declared below */
start refactoring the switch block verilog generation
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#include "mux_library.h"
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#include "module_manager.h"
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#include "rr_blocks.h"
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void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* subckt_dir,
int x, int y,
t_rr_type chan_type,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
int num_segment, t_segment_inf* segments,
t_syn_verilog_opts fpga_verilog_opts);
void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
int pin_index, int side,
int x, int y,
Correction to the explicit Verilog for FPGAs above 2x2
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int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/
Snapshot of progress
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boolean dump_port_type,
bool is_explicit_mapping);
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void dump_verilog_grid_side_pins(FILE* fp,
t_rr_type pin_type, int x, int y, int side,
boolean dump_port_type);
void dump_verilog_switch_box_chan_port(FILE* fp,
t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node,
enum PORTS cur_rr_node_direction);
clean-up warnings Verilog routing generator
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void dump_verilog_switch_box_short_interc(FILE* fp,
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t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node,
int actual_fan_in,
Snapshot of progress
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t_rr_node* drive_rr_node,
bool is_explicit_mapping);
Update VPR7 X2P with new engine
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void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_sb* cur_sb_info,
int chan_side,
t_rr_node* cur_rr_node,
int mux_size,
t_rr_node** drive_rr_nodes,
Stable, is_explicit propagated through the code. Not implemented though except for muxes
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int switch_index,
Include new files in the parameter spreading
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bool is_explicit_mapping);
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int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info, int chan_side,
t_rr_node* cur_rr_node);
int count_verilog_switch_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info, int chan_side,
t_rr_node* cur_rr_node);
void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_sb* cur_sb_info,
int chan_side,
Stable, is_explicit propagated through the code. Not implemented though except for muxes
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t_rr_node* cur_rr_node,
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bool is_explicit_mapping);
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int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info);
int count_verilog_switch_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_sb cur_sb_info);
void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
t_sb* cur_sb_info,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
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t_syn_verilog_opts fpga_verilog_opts,
Stable, is_explicit propagated through the code. Not implemented though except for muxes
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boolean compact_routing_hierarchy,
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bool is_explicit_mapping);
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clean-up warnings Verilog routing generator
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void dump_verilog_connection_box_short_interc(FILE* fp,
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t_cb* cur_cb_info,
Snapshot of progress
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t_rr_node* src_rr_node,
bool is_explicit_mapping);
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void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
Stable, is_explicit propagated through the code. Not implemented though except for muxes
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t_rr_node* src_rr_node,
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bool is_explicit_mapping);
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void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_cb* cur_cb_info,
Stable, is_explicit propagated through the code. Not implemented though except for muxes
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t_rr_node* src_rr_node,
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bool is_explicit_mapping);
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int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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const RRGSB& rr_gsb, enum e_side cb_side);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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Update VPR7 X2P with new engine
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int count_verilog_connection_box_interc_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_rr_node* cur_rr_node);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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const RRGSB& rr_gsb, enum e_side cb_side);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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Update VPR7 X2P with new engine
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int count_verilog_connection_box_one_side_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
int num_ipin_rr_nodes,
t_rr_node** ipin_rr_node);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
2019-06-08 21:11:22 -05:00
int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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const RRGSB& rr_gsb, t_rr_type cb_type);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
2019-06-08 21:11:22 -05:00
Update VPR7 X2P with new engine
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int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
int num_ipin_rr_nodes,
t_rr_node** ipin_rr_node);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
2019-06-10 13:50:10 -05:00
const RRGSB& rr_gsb, t_rr_type cb_type);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
2019-06-08 21:11:22 -05:00
Update VPR7 X2P with new engine
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int count_verilog_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_cb* cur_cb_info);
int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info,
t_cb* cur_cb_info);
void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir, char* subckt_dir,
t_cb* cur_cb_info,
Stable, is_explicit propagated through the code. Not implemented though except for muxes
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boolean compact_routing_hierarchy,
Include new files in the parameter spreading
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bool is_explicit_mapping);
Update VPR7 X2P with new engine
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refactoring Verilog generation for routing channels
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void print_verilog_routing_resources(ModuleManager& module_manager,
t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* subckt_dir,
const t_arch& arch,
const t_det_routing_arch& routing_arch,
int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_ivec*** LL_rr_node_indices,
t_rr_indexed_data* LL_rr_indexed_data,
const t_fpga_spice_opts& FPGA_SPICE_Opts);
Update VPR7 X2P with new engine
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refactored routing module generation and verilog writing
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void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const t_det_routing_arch& routing_arch,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);
void print_verilog_unique_routing_modules(ModuleManager& module_manager,
const DeviceRRGSB& L_device_rr_gsb,
const t_det_routing_arch& routing_arch,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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#endif