* Bug: In AutoSegment::canReduce(), in the repair stage, segments are
allowed to go beyond their GCell bondaries, so global segments can
end up in zero length. So now allow globals less than one P-Pitch
to be flagged as reduced.
* Bug: In AutoSegment::isMiddleStack(), systematically reject non-canonical
segment. If it is non-canonical, then is aligned with a canonical one.
Then we will perform the check on it.
There seems to be another porblem of update of the length of the
associated TrackElement, the increase of size of the non-canonical is
not taken into account. This is enough to prevent the problem to
arise but we should invsetigate further.
* Hack: In AutoSegment::canMoveUp(), prevent segment id:6378409 to be
moved up so the last antenna effect is avoided. This is not a clean
way to do it.
* Change: In GdsStream::_gdsLayerTable, use a map<> instead of a vector<>,
use a combined value of the layer index and the datatype as index.
(index = (layer<<16) + datatype.
This allow for layers that are represented by a pair of (layer,datatype)
with same layer and different datatypes.
* Change: In GdsStream::gdsToLayer(), now have two parameters, the layer
and the datatype.
* Change: In Katana::PowerRails, in TerminalNetlist cells instances,
the ordinary nets components where generating obstacles, leading
to stupid cross blockages between the obstacle generated by the
component supporting the routing pad and the RP itself.
Now only take into account supplies and clocks (any layers)
and blockage layers.
Fix symbolic benches.
* Change: In Katana::Manipulator::moveUp(), the "reserve" value was
of 0.5 for pivot up and locals, now set it to 1.0, like in all
other cases ("reserve" is the number of free tracks that is
needed to allow the move up, in addition the the length being
moved up).
Fix routing convergence on the MIPS pipeline bench.
* Bug: In CRL::GdsParser(), the table of GDS layer was limited to 64,
which is the maximum, according to the reference. But it is no
longer true. Extend to 256.
This was leading to GDS files missing some layers.
* Bug: In TrackSegment::isMiddleStack(), formerly, all global segments
where discarted. But in the routing repair stage, segments can go
*outside* their GCell boundaries, allowing globals to became of
null length.
Hence, for global, we now also check the wirelength.
* Change: In cumulus/plugins.chip.chip.doConnectCore(), do not use the
feature of the HTree to connect the root buffer straight to the
corona pin. It prevents the router to insert a diode when those
wires are too long. So let the standard router manage them.
Should add diode insertions in HTree.connectHTrees() later.
* Bug: In Track::repair(), when a same net gap has been found and closed,
we display a warning. We display the two segments fused, but when it's
the two first, we must not use index "i-1" (with i=0) ...
* Bug: In cumulus/plugins.chip.powerplane.Builder._connectHTree(),
when building the stacked VIAs over the corona Pin and the
root buffer RoutingPad, pass the GaugeConf.HAccess flag so the
stack stops at METAL4 (top horizontal layer).
Before we where also adding a VIA up to METAL5 which was unused
and caused a minimal area violation.
* Change: In AutoSegment::isMiddleStack(), after checking for obvious
non-candidates, relies on axis-to-axis wirelength instead of topological
criterions. We will not be able to account all the topologies that
may cause problem. So consider every segment whose length is below
one perpandicular pitch.
* Change: In cumulus/plugins.block.macro, the METAL2 blockage was
allowing horizontal tracks to be used but the METAL3 blockage
was conflicting with the end of the perpandiculars.
The router was not able to manage that, so we slightly expand
the METAL2 blockage to encompass the unreachable track.
For the same reason, add a METAL4 blockage over METAL2.
* New: In cumulus/plugins.chip.pads, add METAL5 jumpers on all wires
going to/from the I/O pads on the East & West side. This is a
quick hack as:
1. We should put it also on North/South, but no violation
happens here.
2. We should put it on *ouput* wire only (for only those are
connected to transistors gates).
* New: In cumulus/plugins.chip.macro, put jumpers on the East side
connectors for the SRAM block. Also a quick hack, not robust for
anything else than the SRAM.
In Anabatic::AntennaProtect, when we cannot insert enough diodes
under a wire cluster. Which makes it likely very long and over an
area where diodes cannot be inserted (chip border close to I/O pads
or over a macro-block). Request extra diode insertion on it's
connecting RoutingPad clusters.
* New: In Anabatic::DiodeCluster, add a "forced diode" counter for
extra diodes inertions. Only used in the DiodeRps derived class.
* New: In Anabatic::DiodeCluster, add support for a cluster to know
it's neighbors. Stored as indexes of the table being built in
Anabatic::antennaProtect(Net*).
* New: In Anabatic::antennaProtect(Net*), when builing the WireCluster,
also find it's neigbors. Store the index of the cluster a segment
belongs to in clusterSegments.
* Change: In cumulus/plugins.Block.getLeafUnder(): formerly, we where
using the cut-lines (x/y) to locate which leaf a point is under.
But in case of incomplete tree, it is difficult to manage.
Now we chosse the leaf according to the distance to the center
of the leaf area. Choose the shorter, of course.
This solve the H-Tree DFF bad assignment around the PLL (top
right corner) in LS180.
* Bug: In Cumulus/plugins.block.Block, re-order Etesian tool creation
and virtual net flattening. Must investigate later why it is so
sensitive to at least warn/stop cleanly.
* Bug: In Katana::GlobalNetTable::getRootNet(), look for all fixed nets,
not only supplies and clocks. There may be some as now H-Trees are
not limited to clocks.
Should solve ao68000 short circuit cases.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectHTree(), is was
previously assumed that a net manged by a H-Tree was always coming from
the outside (i.e. a clock or a reset signal).
It is no longer the case, for example with the PLL internally generated
clock.
So prune internal signals in this method.
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
* New: In CRL::GdsStream::xyToPath(), now manage BGNEXTN & ENDEXTN for
PATHTYPE 4.
The begin/end Contact are created to use exactly the area of the
extension. Otherwise there were overspill when the size of the
extension is greater than the width of the path. Also need to do
a sligth shift if the extension is an odd number of foundry grid.
This fix the offgrid problems.
* Bug: In cumulus/plugins.macro.Macro.__init__(), stick out the rigth number
of pitches on North & East sides (never tested before).
* New: In cumulus/plugins.macro.Macro.__init__(), manage layer change
if the terminal is not in the preferred routing direction. Use BigVia
and put at least two cuts.
* New: In Anabatic::DiodeWire, use "antennaDiodeMaxWL" to compute the number
of diodes to insert in a wire only cluster. Use boxes instead of segments
to define the area as segments can be splitted by the diodes inserteds
at the DiodeRps stage.
* New: In DiodeWire::createDiodes(), specific diode insertion method.
Try to instert first in long horizontal wires.
Split "antennaMaxWL" into :
* "etesian.antennaGateMaxWL" : max length *without* any diode.
* "etesian.antennaDiodeMaxWL" : max length that *one* diode can support.
Jean-Paul Chaput
Luke Kenneth Casson Leighton