It doesn't have any effect on real hardware, and by caching the value we
pretended it did.
Fixes#564
Change-Id: I9f4e2cc8abddee61435bbd8d992cbff971a0c28d
Signed-off-by: Tim Newsome <tim@sifive.com>
Add `riscv info` command. Final output is "TCL format" and looks like this:
```
hart.xlen 64
hart.trigger_count 4
dm.abits 6
dm.progbufsize 2
dm.sbversion 0
dm.sbasize 0
dm.sbaccess128 0
dm.sbaccess64 0
dm.sbaccess32 0
dm.sbaccess16 0
dm.sbaccess8 0
```
* Add `riscv info` command.
This command displays some basic information that OpenOCD has detected
about the target. The output is displayed in YAML so it can easily be
parsed. Example of current output:
```
Hart:
XLEN: 32
trigger count: 4
Debug Module:
abits: 6
progbufsize: 2
sbversion: 0
sbasize: 0
sbaccess128: 0
sbaccess64: 0
sbaccess32: 0
sbaccess16: 0
sbaccess8: 0
```
Change-Id: If920c083ff6ec9f482c50f913cd8ceaa62461217
Signed-off-by: Tim Newsome <tim@sifive.com>
* Disable workflow inherited from upstream.
Change-Id: Ifc5ed1b4f5ec2278b8bcf3279c9fd462e469fefa
Signed-off-by: Tim Newsome <tim@sifive.com>
* Switch from YAML to TCL "set array" input format.
Change-Id: I3833210e5bf6d7cffc9934c04ec5201ae7732ad8
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove indent in `riscv info` output.
That was getting a little too cute, and probably more confusing than
helpful.
Change-Id: Ie51416f53ab4b69294962f0565767d370db82867
Signed-off-by: Tim Newsome <tim@sifive.com>
The use of 'void *' makes the pointer arithmetic incompatible with
standard C, even if this is allowed by GCC extensions.
The use of 'void *' can also hide incorrect pointer assignments.
Switch to 'uint8_t *' and add GCC warning flag to track any use of
pointer arithmetic extension.
Change-Id: Ic4d15a232834cd6b374330f70e2473a359b1607f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5937
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This lets a user see exactly what period of time was sampled, without
having to guess how much time the target was ignored in between bursts.
Change-Id: I5c0639528636bf1a88f249be3ba59bec28c001e2
Signed-off-by: Tim Newsome <tim@sifive.com>
* Allow riscv_semihosting without 16 bit access to memory with instrustions
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* rename *_by_any_size to riscv_*_by_any_size
Used histogram diff strategy, which was much better than the default.
Conflicts:
doc/openocd.texi
src/flash/nor/fespi.c
src/jtag/drivers/libjaylink
src/rtos/rtos.c
src/target/riscv/batch.c
src/target/riscv/encoding.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/target.c
tcl/target/gd32vf103.cfg
Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
The commit b68674a1da ("Upstream tons of RISC-V changes.") was
proposed well before commit 3ac010bb9f ("Fix debug prints when
loading to flash"), but the merge got in different order.
After latest merge, the master branch fails to compile.
Fix the compile error.
Change-Id: Ia3bd21d970d589343a3b9b2d58c89e0c49f30015
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5856
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.
Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.
I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.
Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
* Do not throw error if RISC-V tselect unimplemented
A RISC-V hart without Trigger Module may not implement any of the
associated CSRs such as tselect according to the specification.
riscv_enumerate_triggers previously threw an error in this case, but
only on the first invocation due to r->triggers_enumerated being set
regardless of this. Due to the propagation of this error condition to
disable_triggers and riscv_openocd_step, such a hart would remain
halted after the first 'step' (or 'continue') of a debug session.
This problem can be reproduced with the Ibex RISC-V CPU when
the DbgTriggerEn parameter is set to zero.
This commit changes the behavior of riscv_enumerate_triggers to
return ERROR_OK when tselect was not readable. This fixes the
described malfunction.
Change-Id: Ie813cb119b03702fe708801b5f3581f9bf337243
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
* Add debug message if RISC-V tselect not readable
Change-Id: Ic3ad5bff9de5c50142cad983f351ce0099cec5c8
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
* RISC-V triggers: continue if tselect is unreadable
In riscv_enumerate_triggers, even if for one hart tselect cannot be
accessed, other harts might provide trigger support. For this reason,
"continue;" is the appropriate action on a read failure of tselect,
which indicates that triggers are not implemented, instead of
"return ERROR_OK;".
Change-Id: Ied56f3e237b76195a15bfde159532eda9d347d21
Signed-off-by: Tobias Kaiser <kaiser@tu-berlin.de>
* Add memory sampling feature.
Currently only gets 10 samples per second, but the overall scaffolding
looks like it works.
Change-Id: I25a2bbcba322f2101c3de598c225f83c902680fa
* Basic memory sample speed-ups.
977 samples/second.
Change-Id: I6ea874f25051aca1cbe3aa2918567a4ee316c4be
* Add base64 dumping of sample buffer.
We can't just dump raw data, because the API we use to get data to the
"user" uses NULL-terminated strings.
Change-Id: I3f33faaa485a74735c13cdaad685e336c1e2095f
* WIP on optimizing PC sampling.
1k samples per second on my laptop, which is roughly double what it was.
Change-Id: I6a77df8aa53118e44928f96d22210df84be45eda
* WIP
Change-Id: I4300692355cb0cf997ec59ab5ca71543b295abb0
* Use small batch to sample memory.
5k samples/second. No error checking.
Change-Id: I8a7f08e49cb153699021e27f8006beb0e6db70ee
* Collect memory samples near continuously.
Rewrite OpenOCD's core loop to get rid of the fixed 100ms delay.
Now collecting 15k samples/second.
Change-Id: Iba5e73e96e8d226a0b5777ecac19453c152dc634
* Fix build.
Change-Id: If2fe7a0c77e0d6545c93fa0d4a013c50a9b9d896
* Fix the mess I left after resolving conflicts.
Change-Id: I96abd47a7834bf8f5e005ba63020f0a0cc429548
* Support 64-bit address in memory sampling.
* Support sampling 64-bit values.
* Better error reporting. WIP on 64-bit support.
* Speed up single 32-bit memory sample.
21k samples/second.
* WIP on review feedback.
Change-Id: I00e453fd685d173b0206d925090beb06c1f057ca
* Make memory sample buffers/config per-target.
Change-Id: I5c2f5997795c7a434e71b36ca4c712623daf993c
* Document, and add bucket clear option.
Change-Id: I922b883adfa787fb4f5a894db872d04fda126cbd
Signed-off-by: Tim Newsome <tim@sifive.com>
* Fix whitespace.
Change-Id: Iabfeb0068d7138d9b252ac127d1b1f949cf19632
Signed-off-by: Tim Newsome <tim@sifive.com>
* Document sample buffer full behavior.
Change-Id: Ib3c30d34b1f9f30cf403afda8fdccb850bc8b4df
Signed-off-by: Tim Newsome <tim@sifive.com>
* Actually clear the sample buffer in dump_sample_buf.
Change-Id: Ifda22643f1e58f69a6382abc90474659d7330ac5
Signed-off-by: Tim Newsome <tim@sifive.com>
* Use compatible string formatting.
Change-Id: Ia5e5333e036c1dbe457bc977fcee41983b9a9b77
Signed-off-by: Tim Newsome <tim@sifive.com>
* Improve riscv expose_[csrs|custom] commands
* Add option to specify custom name for registers.
* Allow to call commands multiple times without loss of previous data.
* Make sure the commands can only be used in the config phase (before "init").
* Validity checks and warnings.
* Change commands to be per target.
* Fix memory leaks.
* Also fix unrelated memory leaks to keep valgrind happy.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* fixes after review
* improve error message
This seems to be completely unused in these two files. It was probably
accidentally copied from riscv-011.c, where it is used.
Change-Id: I3f7ad8b2d26b005d3ea4438e2b3ec46a6c801792
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
These comments appear to have been copied from riscv-011.c, for which
they are accurate. However, it makes no sense to also have them in
riscv.c, because 1) none of the things described are actually in
riscv.c; and 2) riscv-013.c has an entirely different code structure,
meaning everything in the comment is an implementation detail of
riscv-011.c. Remove the copy in riscv.c and just leave the one in
riscv-011.c.
Change-Id: I2873af1522482681325525040b3caad2ddddce9d
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* Allocate RISC-V arch_info during target creation
* Ensured that target->arch_info is allocated as soon as the
target is created. Needed so that per-target config commands
(e.g. "riscv set_mem_access") can be executed also in the
OpenOCD's config phase (before calling "init").
* Added several assert()'s for safety.
Signed-off-by: Jan Matyas <matyas@codasip.com>
* Removed a TODO comment
* Allow to put breakpoints in memories without 16 bit access
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* tmp
* tmp
* tmp
* read/write by any size for breakpoints
* fix style for checkpatch
* Add flexible selection of memory access methods, detection of aampostincrement.
New configuration command introduced: "riscv set_mem_access".
It allows to specify which RISC-V memory access methods (progbuf,
sysbus and/or abstract access) should be tried and in which order
of priority.
Command "riscv set_prefer_sba" is left and works in backward
compatible way, but is marked as deprecated.
First time abstract memory access is executed, it is tried with
set aampostincrement bit. If the abstract command fails or the
address is not incremented correctly, aampostincrement will not
be used for any subsequent accesses.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* remove unnecessary variable
* fix doc
The function free() can be called with a NULL pointer as argument,
no need to check the argument before. If the pointer is NULL, no
operation is performed by free().
Remove the occurrences of pattern:
if (ptr)
free(ptr);
In target/openrisc/jsp_server.c, an error is logged if the ptr was
already NULL. This cannot happen since the pointer was already
referenced few lines before and openocd would have been already
SIGSEGV in that case, so remove the log.
Change-Id: I290a32e6d4deab167676af4ddc83523c830ae49e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5809
Tested-by: jenkins
* WIP, apply stash with conflicts.
Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31
* Fix conflict resolution problems.
Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238
* Add repeat_read command.
Only implemented for sba v1 right now, and poorly tested at that.
Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b
* Hide bogus address in repeat_read
Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa
* WIP make repeat read work with progbuf.
Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79
* WIP
Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d
* Fix error handling when increment is non-zero.
Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a
* Correctly(?) handle failures when increment is 0.
I'm not 100% convinced that this ensures every read value shows up in
the output, but it ought to work.
Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa
* Don't crash when asked to read no data.
Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05
* Remove unnecessary comment.
Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f
* Document `riscv repeat_read`.
Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
Technically that might be OK, but in practice it probably indicates
something went wrong somewhere. Before this change OpenOCD would crash
if it happened.
Change-Id: I2500ba67ec282915dcf2b2488f2aac9fbfdb23a3
This logic is a little tortured, but it still passes the semihosting
tests that were the cause for the recent rewrite.
Change-Id: Ic6760bb068621ab2a49feb0cf3998fc6957b5cfc
* Accommodate users setting custom triggers.
RISC-V hardware supports many more triggers than gdb can communicate to
OpenOCD. Accommodate users that set triggers by writing tdata* directly,
by disable/step/reenable when a user has done that.
Note that users must set dmode in tdata1 for this behavior to work
properly. Triggers with dmode=0 are assumed to be set and handled by the
software that is being debugged.
Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066
* Enumerate triggers when resuming from a trigger
Otherwise when we connect to a target that's already halted due to a
trigger, we won't correctly step past it.
Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c
* Also disable/reenable triggers around single step.
Gdb is smart enough to disable/step/resume if it set the triggers, but
if a user set them manually it also needs to happen.
Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f
* Fix whitespace.
Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
* WIP making semihosting work with -rtos hwthread.
Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e
* More WIP.
Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb
* Fix halting due to a trigger.
Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad
* Fix multicore semihosting without halt groups.
Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4
* WIP
Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40
* Fix single core semihosting.
This was the last bug!
Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28
* Fix whitespace.
Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types OPEN_BRACE -f {} \;
Change-Id: I6d1356ed11e2699525f384efb7556bc2efdc299f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5628
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Long strings are split across few lines; usually split occurs at
the white space between two words.
Check that the space between the two words is still present.
While there, adjust the amount of space between words.
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types MISSING_SPACE -f {} \;
Change-Id: I28b9a65564195ba967051add53d1c848c7b8fb30
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5620
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
This fixes a bug where we read PC and marked it cached without actually
updating the cached value. The DPC value was correctly marked as valid
and updated.
Change-Id: Id6d3e94a96b981688b06f7f4a998019f2c02f6f5
* Cache accesses through riscv_[sg]et_register.
This helps a lot with the address translation code, which checks satp
over and over again. Now satp is only read once per halt. It should also
help in a few other cases (but I don't have a good test setup to really
measure the impact).
Change-Id: I90392cc60d2145a70cf6c003d6a956dc9f3c0cc4
* Fix whitespace.
Change-Id: I05c5342d8a461cd8c618a3f60296925e9e84643f
* Don't read registers that we know don't exist.
Change-Id: Ie5c6226b3d4ecb6cf8f0d8954a52fda88e6e5bdd
If we return failure, then the caller will think something's wrong. But
it could very well be that the hardware doesn't have SATP, in which case
we should just report that the MMU is disabled.
This fixes a bug where flashing wasn't using the target algorithm
because allocating a work area failed.
Change-Id: I16e8e660036d3f8584c0b17e842c4ec8961a8410
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
the same semihosting handlers chain is declared twice:
1. in src/target/armv4_5.c
2. in src/target/riscv/riscv.c
to make it simpler we moved the declaration into
'src/target/semihosting_common.c' under semihosting_common_handlers[].
then we used this into both of armv4_5.c and riscv.c
Change-Id: If813b3fd5eb2476658f1308f741c4e805141f617
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5473
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)
Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tim Newsome
Antonio Borneo
Samuel Obuch
Tobias Kaiser
Tom Hebb
Jan Matyas
Jiuyang Liu
Tommy Murphy
Tarek BOCHKATI
Tomas Vanek