It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)
Fixes#757.
Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
breakpoint_add should use rtos only if request is done by gdb.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus
set to 0), accessing any fp register results in a hang (any abstract
command timeouts, untill the board is rebooted).
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
* gdb_server: Improve info message.
Add target name and state to "Not running when halt was requested"
message.
Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd
Signed-off-by: Tim Newsome <tim@sifive.com>
* rtos/hwthread: Nicer debug message in hwthread_update_threads()
Change-Id: Ia5931a772476a2ae186ed87cd70d7e4be2f196fb
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
E.g. the Zve* vector extensions have all the same registers as the full
V extension, but leaves misa.V clear.
Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Prep work for handling unavailable harts.
Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Use match field for trigger
The watchpoint cannot capture all data modifications only through the
trigger of ANY SIZE and EQUAL, and an error will occur. This patch
accommodates watchpoints by adding more types of matches
Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a
Signed-off-by: Xiang W <wxjstz@126.com>
* Add variable type trigger support
Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1
Signed-off-by: Xiang W <wxjstz@126.com>
* remove trailing whitespace
Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84
Signed-off-by: Xiang W <wxjstz@126.com>
* update triggers enumerate
Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()
Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>
* Comment code more clearly.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove extra tab
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery
Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
* target/riscv Ensure HART_INDEX_DIRTY does not have side effects
Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).
Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
* target/riscv: Correctly set target->state in deassert_reset
This bug didn't lead to problems, but it would with some upcoming
changes.
Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb
Signed-off-by: Tim Newsome <tim@sifive.com>
* Keep debug_reason in sync with state
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* [riscv] step operation handler should respect handle_breakpoints parameter
When step operation is requested the OpenOCD frontend (like gdb server
or TCL server) has an option to control how existing breakpoints are
handled upon step.
Some OpenOCD frontends (like gdbserver) may choose to disable special
handling of existing breakpoints - thus handle_breakpoints is set to 0,
while others (like TCL server) expect target handler to temporary
disable the matching breakpoint to allow the step operation to complete
successfully.
In the current implementation handle_breakpoints parameter was ignored
by target-specific handler. Thus, the following sequence of commands:
```
halt
bp <current_pc> 4
step
```
Resulted in *step* operation to not change PC because of bp match.
This commit addresses this issue.
* Adjusted calls to logging facilities (addressed review comments)
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
* Properly track selecting multiple harts at once.
use_hasel is a bit of a hack.
Change-Id: Ia589ebc16bca32038d915df9988361b88e940917
Signed-off-by: Tim Newsome <tim@sifive.com>
* Clarifying comment.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Rename set_hartsel to set_dmcontrol_hartsel
Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850
* Make set_dmcontrol_hartsel() more idiomatic.
Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486
* Use constant for multiple harts instead of -1.
Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
I'd rather see "these 10 lines were repeated 100 times" than "these 100
lines were repeated 10 times."
Change-Id: I88fcf86b10c5fb0ba1d19b21fe054065da90fedd
Signed-off-by: Tim Newsome <tim@sifive.com>
Also add an early exit for if any harts are unavailable.
Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8
Signed-off-by: Tim Newsome <tim@sifive.com>
This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).
This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.
Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
According to RISC-V External Debug Support Version 0.13.2 (paragraph
3.12.6), cmderr field contains a valid value only if busy is 0, so it is
incorrect to analize it on timeout.
Requested in https://review.openocd.org/c/openocd/+/6964.
I'm making the change here so I have a chance to test it properly before
pushing it upstream.
A nice effect of this change is that we avoid some unnecessary polling
early on when gdb is connecting and we would poll once every time we
send gdb a qXfer packet.
Change-Id: I4bdb9f05839e8c1e01ff6dde49d6589595418095
Signed-off-by: Tim Newsome <tim@sifive.com>
Otherwise OpenOCD simply doesn't work without giving any indication why.
Change-Id: I21703fc1a0d9bed2f59da95f8a8395fe139484a4
Signed-off-by: Tim Newsome <tim@sifive.com>
* Don't read dmcontrol to set hartsel
We already know what dmcontrol should be. This addresses a long-standing
TODO. In a toy test, this reduced the number of scans by 10+%. (Most of
those are probably in poll(), so don't actually affect perceived
performance.)
Change-Id: I18e5ca391f0f5fb35f30d44dfef834e5a66aee20
Signed-off-by: Tim Newsome <tim@sifive.com>
* Make code easier to read
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
It was a left-over from `-rtos riscv` and isn't used.
Change-Id: Ie7e380600cd1331c6d382f654474270efad9f127
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Tim Newsome
Evgeniy Naydanov
Xiang W
Dolu1990
Anatoly Parshintsev
mrv96
Dmitry Ryzhov
Evgeniy Naydanov