fbe2980eb7
MemTest64 passes.
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Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
2017-10-17 11:15:51 -07:00
d94b38279a
Memtest{16,32} pass.
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Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-16 21:08:59 -07:00
7ec7bc32fe
At least some memory writes work.
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Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
2017-10-13 12:50:02 -07:00
e7bb815e87
Register read/write might be working.
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Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
2017-10-12 14:38:52 -07:00
94e8250713
WIP; doesn't work.
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Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-12 11:45:52 -07:00
77802af655
Remove duplicate progbuf size variable.
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Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
2017-10-10 16:27:51 -07:00
f06aaa9058
Merge pull request #123 from riscv/fast_rbb
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Add read buffer to bitbang, improving performance.
2017-10-09 11:06:20 -07:00
ed415c3cb6
Merge pull request #129 from riscv/minor_revert
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Revert this LOG_INFO to LOG_DEBUG.
2017-10-09 11:06:08 -07:00
2da7820833
Revert this LOG_INFO to LOG_DEBUG.
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Change-Id: I75dd7667a542aa1c6ea10f97fe1e00dd1ecba69d
2017-10-08 11:41:55 -07:00
7aafd61953
Clean up this JTAG debug code.
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Change-Id: Ie7c773b98271d11085d5e50c40b64990710de387
2017-10-06 13:55:52 -07:00
d5836dceff
Merge pull request #126 from riscv/compile
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Fix compile warnings.
2017-10-04 16:07:40 -07:00
24658db50e
Fix compile warnings.
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Partly fixes #124 .
Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
2017-10-04 16:02:30 -07:00
77680cb23d
Merge pull request #125 from riscv/cleanup
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Revert ae74097f
2017-10-04 15:48:34 -07:00
916759e0de
Revert ae74097f (extra ftdi debug).
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Instead it makes more sense to push the debug changes to jtag/core.c.
Change-Id: I73bafa2a054e1f72b7752cfbce9ffc14303fc4c4
2017-10-04 15:44:07 -07:00
28eb10f43d
Ensure the buffer doesn't overflow.
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Tested with a variety of prime buffer sizes.
Change-Id: I2b4835d46adf4c971111da88e8de4b46eb8dad41
2017-10-04 15:23:38 -07:00
abe7eba25a
Merge pull request #118 from riscv/priv
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Fix priv access
2017-10-04 12:52:21 -07:00
1b11d579ea
Add read buffer to bitbang, improving performance.
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This reduces the time for one testcase where OpenOCD connects to a
simulator from 12.30s to 5.35s!
Running all our tests went from 13m13s to 3m55s.
Change-Id: I7dc774e1e0f5752905ac4318fd9b85b930374a05
2017-10-03 15:38:31 -07:00
a3c26250bf
Merge pull request #116 from riscv/multigdb
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Fix trigger code to work with multi-gdb mode instead of RTOS mode
2017-10-03 11:53:58 -07:00
e94c809ce4
Merge pull request #120 from gnu-mcu-eclipse/riscv-warnings
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Silence some clang warnings
2017-10-03 11:27:57 -07:00
2f6dd2a4b5
Merge pull request #121 from gnu-mcu-eclipse/riscv-reorder
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flash/nor/Makefile.am: keep files in lexicographical order
2017-10-03 11:26:32 -07:00
066ce338d8
flash/nor/Makefile.am: lexicographical order
2017-10-03 00:48:15 +03:00
f9f303923e
target/riscv/asm.h: use tab for indentation
2017-10-03 00:36:22 +03:00
f5a69e547f
target/riscv/program.c: fix clang warning
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- I'm not sure I understand the logic behind the original statement,
but on macOS it fails to compile.
2017-10-03 00:23:14 +03:00
728a617bd4
target/riscv: Silence -Werror=return-type
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- clang compains about the functions not returning a value
2017-10-03 00:17:57 +03:00
12bb3a4fd4
Merge pull request #119 from gnu-mcu-eclipse/riscv-upd
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Update to master (Aug 10, 2017)
2017-10-02 11:56:19 -07:00
7dc04d7d0a
Merge commit '7719e9618e753ac41a46a2488dfba549ac578891' into riscv-upd
2017-10-01 01:57:46 +03:00
e64bb8c44a
Fix priv access on 0.13.
2017-09-30 14:15:37 -07:00
6795270a8e
Make priv readable in 0.11.
2017-09-30 13:31:57 -07:00
1083352576
Share register numbers between 0.11 and 0.13.
2017-09-30 13:13:03 -07:00
51f73a6769
Fix triggers for multi-gdb mode.
2017-09-26 15:40:49 -07:00
744894e965
Better debug messages.
2017-09-26 15:40:41 -07:00
a854089fd1
Merge pull request #114 from riscv/reset
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Reset
2017-09-25 11:05:42 -07:00
f0195868d3
Fall back on ndmreset if hartreset is unsupported.
2017-09-21 14:53:12 -07:00
fe36097ff8
Fix reset for multicore.
2017-09-21 12:42:40 -07:00
848fe0ffcf
Cleaning up single-hart reset.
2017-09-19 17:41:52 -07:00
4e701669b7
Merge pull request #113 from riscv/macos_build
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Add clang build
2017-09-19 14:11:10 -07:00
fd2d2d0aa3
Merge pull request #91 from riscv/info
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Be more clear in multi-core systems without -rtos
2017-09-19 12:53:02 -07:00
60354cbea2
clang fix, don't allow unaligned uint64_t pointers
2017-09-18 14:56:46 -07:00
ed9a04bde9
Remove unnecessary abs().
2017-09-18 14:35:47 -07:00
0abd94b50c
Make constants unsigned for clang.
2017-09-18 14:23:59 -07:00
702cb0dd46
Another try at 32/64 gcc/clang
2017-09-18 14:05:32 -07:00
604dfa0dcc
Try to fix some clang warnings.
2017-09-18 14:03:33 -07:00
bf737b8985
Remove osx, do 32/64 gcc/clang.
2017-09-18 13:52:49 -07:00
a715500912
Try clang build.
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Travis takes a long time to start OSX builds.
2017-09-18 13:47:03 -07:00
21bd5e7b68
Try OSX build.
2017-09-18 13:37:51 -07:00
157a67a98a
Be more clear in multi-core systems without -rtos
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Don't print out there's a hart with XLEN of 0.
2017-09-18 11:29:14 -07:00
deaf2d7663
Merge pull request #109 from riscv/fextension
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Add support for F extension.
2017-09-15 11:23:57 -07:00
ce20be3d78
Add support for F extension.
2017-09-14 16:23:47 -07:00
1cd8ecfdcd
Merge pull request #107 from riscv/infloop
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Add timeout to another infinite loop.
2017-09-11 12:19:44 -07:00
f9b2549e20
Tell user how to increase timeout.
2017-09-11 12:11:24 -07:00
Tim Newsome
Liviu Ionescu