interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,184 Commits 65 Branches 14 Tags 103 MiB
Commit Graph

54 Commits

Author SHA1 Message Date
Zachary T Welch ef746e27c5 command_t -> struct command 
Remove misleading typedef and redundant suffix from struct command.
 2009-11-13 13:30:50 -08:00
Zachary T Welch 98723c4ecd command_context_t -> struct command_context 
Remove misleading typedef and redundant suffix from struct command_context.
 2009-11-13 13:25:47 -08:00
Zachary T Welch 0f1163e823 target_t -> struct target 
Remove misleading typedef and redundant suffix from struct target.
 2009-11-13 11:58:14 -08:00
Zachary T Welch ac927559c3 target_type_t -> struct target_type 
Remove misleading typedef and redundant suffix from struct target_type.
 2009-11-13 11:58:13 -08:00
Zachary T Welch af949b2531 armv4_5_common_t -> struct arm 
Remove misleading typedef and just use struct arm.
 2009-11-13 11:58:13 -08:00
Zachary T Welch d727f97889 cortex_a8_wrp_t -> struct cortex_a8_wrp 
Remove misleading typedef and redundant suffix from struct cortex_a8_wrp.
 2009-11-13 11:58:13 -08:00
Zachary T Welch 42fb6b8876 cortex_a8_brp_t -> struct cortex_a8_brp 
Remove misleading typedef and redundant suffix from struct cortex_a8_brp.
 2009-11-13 11:58:13 -08:00
Zachary T Welch 53c05c8b1d breakpoint_t -> struct breakpoint 
Remove misleading typedef and redundant suffix from struct breakpoint.
 2009-11-13 11:58:13 -08:00
Zachary T Welch 46fc1d57ac working_area_t -> struct working_area 
Remove misleading typedef and redundant suffix from struct working_area.
 2009-11-13 11:58:12 -08:00
Zachary T Welch 74d09617b9 reg_cache_t -> struct reg_cache 
Remove misleading typedef and redundant suffix from struct reg_cache.
 2009-11-13 11:58:12 -08:00
Zachary T Welch a1971ecacf cortex_a8_common_t -> struct cortex_a8_common 
Remove misleading typedef and redundant suffix from struct cortex_a8_common.
 2009-11-13 11:58:11 -08:00
Zachary T Welch 248448ee3a armv7a_common_t -> struct armv7a_common 
Remove misleading typedef and redundant suffix from struct armv7a_common.
 2009-11-13 11:58:10 -08:00
Zachary T Welch f96d6054e6 swjdp_common_t -> struct swjdp_common 
Remove misleading typedef and redundant suffix from struct swjdp_common.
 2009-11-13 11:58:09 -08:00
Zachary T Welch 42ef503d37 jtag_tap_t -> struct jtag_tap 
Search and destroy the jtag_tap_t typedef.  This also cleans up a
layering violation, removing the declaration from types.h.
 2009-11-13 11:58:04 -08:00
Zachary T Welch cfc4d5c6b7 use COMMAND_HANDLER macro to define all commands 2009-11-13 10:51:45 -08:00
David Brownell 5eb638c71e Cortex-A8: fix indent 
The "remove (forward) declarations" patch goofed indentation on the
"cortexa8_target" struct; fix.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
 2009-11-13 08:45:20 -08:00
Zachary T Welch e997431602 cortex_a8: remove declarations, use static keyword 2009-11-11 11:53:22 -08:00
David Brownell a81df55f39 Cortex-A8: use the new inheritance/nesting scheme 
Use target_to_armv7a() etc, replacing needless pointer traversals.
Stop using X->arch_info scheme in most ARMv7-A and Cortex-A8 code.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
 2009-11-05 22:04:13 -08:00
Øyvind Harboe 1ebdc24494 cortex_a8: add mrc mcr interface. 
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
 2009-11-05 23:56:37 +01:00
Øyvind Harboe af66678c9a target: remove unused interface fn that clutters code 
The quit entry point was not being invoked. Just a source
of confusion at this point. XScale ran 100x reset upon
quit, but that code made no sense, wasn't commented
and never invoke.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
 2009-11-05 09:07:56 +01:00
Øyvind Harboe acff2521fb debug interface: get rid of unused pre_debug fn 
Removing unused code makes it much less mysterius.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
 2009-11-05 09:05:10 +01:00
Yauheni Kaliuta 6a2fd7cad5 Cleanup: nuke trailling whitespaces 
Signed-off-by: Yauheni Kaliuta <y.kaliuta@gmail.com>
 2009-10-13 19:16:57 +02:00
mlu 16742b529b It is not possible to invalidate I-Cache on memory writes while the target is running 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2795 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-10-02 16:50:42 +00:00
mlu 49f3497bfa Make sure that DSCR_DTR_RX is not full before writing 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2794 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-10-02 16:44:16 +00:00
mlu 1b90a9f5eb More error reporting in Cortex_a8 execute_opcode 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2793 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-10-02 16:39:50 +00:00
mlu 84dabdcc72 Added asser_reset and deassert_reset for cortex_a8 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2792 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-10-02 16:37:22 +00:00
mlu c74ede4248 Added asser_reset and deassert_reset for cortex_a8 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2791 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-10-02 16:36:03 +00:00
dbrownell 86a7d813a1 Remove annoying end-of-line whitespace from most src/* 
files; omitted src/httpd


git-svn-id: svn://svn.berlios.de/openocd/trunk@2742 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-21 18:40:55 +00:00
mlu 781997f556 Avoid cache invalidation when writing to hardware debug registers 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2733 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-19 14:50:18 +00:00
mlu 7b3be0e21e Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.c 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2728 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-18 15:11:46 +00:00
mlu 45f03dd9b5 Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASE 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2716 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-16 18:17:26 +00:00
mlu 45674af63a Check return values to avoid infinite wait in loop on error. 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2709 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-14 22:41:47 +00:00
mlu d4e4d65d28 Cache invalidation when writing to memory 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2708 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-14 22:36:27 +00:00
mlu c4ee12ea77 Fix argument passing in cortex_a8_write_cp. 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2701 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-13 13:57:50 +00:00
mlu f6a5749c1b Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state. 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2677 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-08 15:31:24 +00:00
mlu 2c76cd7171 Improved handling of instruction set state, helps for debugging Thumb state. 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2674 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-07 20:19:17 +00:00
oharboe 81b57a3fb6 Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode. 
By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-04 08:22:02 +00:00
oharboe 51be978b43 Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR register 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2666 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-09-04 05:20:45 +00:00
oharboe 327ba6cb0a Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> cortex-a8: Wait for the CPU to be halted/started 
With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-26 19:25:44 +00:00
oharboe 01000e988a Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Only dap_ap_select when we are going to do a memory access 
in the fast reg case.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-26 19:23:35 +00:00
oharboe 56a04a3413 Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into 
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-26 19:21:26 +00:00
oharboe f36d0083de Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function. 
git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-26 19:20:25 +00:00
oharboe 56b346447b Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Before executing a new instruction wait for the previous 
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-26 19:16:08 +00:00
ntfreak 7a1ac49ac9 - fix build warnings 
- add svn props to recently added files armv7a.[ch]

git-svn-id: svn://svn.berlios.de/openocd/trunk@2618 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-25 12:19:44 +00:00
oharboe 1d0b276c9f David Brownell The rest of the Cortex-A8 support from Magnus: replace the previous 
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from Øyvind, and cleanup from Dave.)

This code has mainly been developed and tested against R1606, it has 
been built and tested against R2294 where it runs but step and resume 
commands are broken due to regression (which should be fixed now).

This code is really written for OMAP3530.  It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection.  The OMAP3530 DAP exposes two memory access ports:

 - Port #0 is connected to L3 interconnect (the main bus) with
   passthrough to the L4 EMU bus ... so it will be used for most
   memory accesses.

 - Port #1 is connected to a dedicated debug bus (L4 EMU), with
   access to L4 Wakeup, and holds the ROM table ... so it must
   be used for most debug and control operations.

The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code.  Having access to another Cortex-A8
implementation would help get that right.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-08-25 06:58:34 +00:00
zwelch f90d8fa45f Remove whitespace that occurs after '('. 
- Replace '([ \t]*' with '('.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2376 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-06-23 22:46:23 +00:00
zwelch 3c2eabd20f Transform 'u32' to 'uint32_t' in src/target 
- Replace '\([^_]\)u32' with '\1uint32_t'.
- Replace '^u32' with 'uint32_t'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2279 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-06-18 07:09:35 +00:00
zwelch f876d5e9c7 Transform 'u16' to 'uint16_t' 
- Replace '\([^_]\)u16' with '\1uint16_t'.
- Replace '^u16' with 'uint16_t'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2277 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-06-18 07:07:59 +00:00
zwelch 86173cdbdd Transform 'u8' to 'uint8_t' in src/target 
- Replace '\([^_]\)u8' with '\1uint8_t'.
- Replace '^u8' with 'uint8_t'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2274 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-06-18 07:04:08 +00:00
zwelch 74df79d4d8 Final step in isolating target_type_s structure: 
- Move definition of 'struct target_type_s' into new 'target_type.h' file.
- Forward delclaration remains in target.h, with comment pointing to new file.
- Replaces #define with #include in source files.


git-svn-id: svn://svn.berlios.de/openocd/trunk@1971 b42882b7-edfa-0310-969c-e2dbd0fdcd60
 2009-05-31 12:38:28 +00:00