Commit Graph

8268 Commits

Author SHA1 Message Date
Karl Palsson 4e0371bf71 hla_target: allow non-intrusive profiling on cortex-m
Leverages the existing work that added profiling via DWT_PCSR.

hla_target doesn't have direct access to the mem_ap for doing a bulk
repeated read, but simply reading the DWT_PCSR register repeatedly is
still ~2 order of magnitude faster than halt/resume.

Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4220
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:31:36 +00:00
Simon Schubert 64b0d5aac0 cortex_m: add profiling function
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc.

Signed-off-by: Simon Schubert <2@0x2c.org>
Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42
Reviewed-on: http://openocd.zylin.com/4211
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:29:59 +00:00
Felipe Balbi 2b44b52478 target: lakemon: implement assert_reset and deassert_reset
We're using an I/O port reset by default. The only board currently
supported (Galileo) doesn't have SRST routed on the JTAG connector.

When using 'reset halt', we must rely on Reset Break because our
adapters don't have support for PREQ#/PRDY# signals.

Tested with Intel Galileo GEN2.

Change-Id: Ia406e31c156f8001717d5b6a08bd03f71de790d3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4016
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:25:34 +00:00
Felipe Balbi 3accbec901 target: quark_x10xx: miscellaneous cleanups
Just some misc cleanups without any functional changes. It's just
easier to read.

Change-Id: I66bee31f297bcbdb8cc4446b774d7714fbaa7c83
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4015
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:25:12 +00:00
Felipe Balbi ffa6b189a0 target: type: fix indentation
No functional changes, cleanup only

Change-Id: I53c422be16d0a4ff157745d31362f6483093e5eb
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4014
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:25:00 +00:00
Felipe Balbi 1ea313e333 target: lakemon: probemode entry isn't instantaneous
When testing with Intel Galileo GEN2 I have noticed a few iterations
where probemode entry took a little longer. At most I had to read
tapstatus twice. This patch uses a loop of up to 100 iterations to
wait for tapstatus to update with PM entry results.

Change-Id: I1c87d7dde715255b3fd2460d299b9493218533fc
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4013
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:24:50 +00:00
Felipe Balbi ea80232c5e target: quark_x10xx: adding missing 'static' keyword
These symbols are only used within this C source file. They don't need
to be exposed to the outside.

Change-Id: Idb04550ecca7f12c3fdc8c6447eeeb871961add3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4012
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:24:27 +00:00
Robert Jordens 43cf6f9b62 digilent_jtag_smt2_nc: add support
The Digilent SMT2 NC is nominally the connector-less version of the
SMT2. But neither the SMT2 configuration nor the HS3 configuration work
for on the Xilinx KCU105 board where the SMT2 NC is used.

Change-Id: Ieb27cbc6d8b0f9c64ef778e4e0c839acc85ec0ef
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4187
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:17:29 +00:00
barthess dc28a6e593 XCF (Xilinx platfrom flash) support.
Change-Id: I4ee6db5f0abdb9fd279cc0edd13f71952a9d295d
Signed-off-by: Uladzimir Pylinski <barthess@yandex.ru>
Reviewed-on: http://openocd.zylin.com/3914
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13 09:13:14 +00:00
Paul Fertser 99b03d3bfb doc: add SVF optional arguments descriptions
Change-Id: I1a3e5b04b6bc4821c4d11c8fcb33b426d6d41bfb
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4314
Tested-by: jenkins
Reviewed-by: Jim Norris <u17263@att.net>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2018-01-13 08:45:35 +00:00
Paul Fertser 12a838c6d4 server: gdb: always print target information in multi-target setups
When multiple targets are declared, it's not always obvious which
target the connection was made for, this can lead to very confusing
errors.

Reported by zjason on IRC.

Change-Id: I52906320394e89cb6cfe82054a3f94b27c999689
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4135
Tested-by: jenkins
2018-01-13 08:44:57 +00:00
Paul Fertser b95e0c13aa flash/startup: make program accept filenames with spaces and other characters
This should allow to process any path names excluding those that have
curly braces.

Change-Id: I87bf9ddede11e2b28d5826878eb1338143f73c03
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4083
Tested-by: jenkins
2018-01-13 08:43:26 +00:00
Paul Fertser 3cb7fd4a60 tools: release.sh: produce only SHA256 hashes
Both MD5 and SHA-1 shouldn't be relied upon since long.

Change-Id: I0dea92fbf0f68b900c0d3a314fb3956d08ba0d48
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3949
Tested-by: jenkins
2018-01-13 08:41:23 +00:00
Paul Fertser 85ac081c22 jtag: drivers: sysfsgpio, bcm2835gpio: remove requirement to have trst or srst
This doesn't seem to make any sense.

Change-Id: I272de0ea3c0e86cc9a798cbd864050aaa597c3f0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3933
Tested-by: jenkins
2018-01-13 08:40:44 +00:00
Paul Fertser fe577e0b63 target: arm: disassembler: decode v6T2 ARM MOV{W,T} instructions
Change-Id: I32cf2669b1b22d4142f30674cf918e36561a885e
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3899
Tested-by: jenkins
2018-01-13 08:36:37 +00:00
Paul Fertser 2420aa00a4 target: arm: disassembler: decode v6T2 ARM ISB instruction
Change-Id: Iaaa54aee6a74f0b250b83c53e7a3fb7c17718920
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3895
Tested-by: jenkins
2018-01-13 08:36:29 +00:00
Paul Fertser c26bbf7a1b target: arm: disassembler: decode v6T2 ARM DSB instruction
Change-Id: Id91b1a87d34982c72f2a8ab46564c961d1fef9dc
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3894
Tested-by: jenkins
2018-01-13 08:36:17 +00:00
Paul Fertser de974eaed3 target: arm: disassembler: add v5T Thumb BLX decoding
Reported by thesourcerer on IRC.

Change-Id: I36d4d95de176a19fdd0bf80d8b419be6ca637e98
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3893
Tested-by: jenkins
2018-01-13 08:36:03 +00:00
Paul Fertser c652f44ca3 flash: startup.tcl: do not disable polling when not exiting
Change-Id: I31b8a8b4519d65d6587207a71eb08dcee8ddd6fd
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4243
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2018-01-13 08:17:21 +00:00
Aleksey Shargalin b34e013965 remote_bitbang_sysfsgpio: fix reset handling
When both SRST and TRST asserted, 'u' is sent to remote bitbang.
Fix for correct handling of such a case

Change-Id: I2a93ff71f5bbae658e6c0c3649a9fbcca2c5a14b
Signed-off-by: Aleksey Shargalin <myokaski@gmail.com>
Reviewed-on: http://openocd.zylin.com/4283
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-13 06:35:55 +00:00
Pushpal Sidhu 133e01d2af board: consolidate st_nucleo_l4 boards
We can now use the generic stlink.cfg which allows for both ST-LINK/V2
and V2-1 debuggers.

Change-Id: I229c6fe5f6a6a4f2d3c787a49939846f102f9e24
Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
Reviewed-on: http://openocd.zylin.com/4313
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-13 06:27:11 +00:00
Ake Rehnman cf2b9cbf5c Added config files for stm8l152 stm8s003 and stm8s105
Change-Id: I26cc401aafac01e5aed8eac605488da5221ffdc2
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/4268
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-12 20:22:46 +00:00
Ake Rehnman a6dea119a3 stlink_usb: Changes to make connect_under_reset work
Leaving mode before closing added
Resolved a collision with JTAG API v1 error/status
checking overwriting SWIM status bytes

Change-Id: I35444ec0e6caace3e072c60085059602f4cdf0a4
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/4265
Tested-by: jenkins
Reviewed-by: Philipp Klaus Krause
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-12 20:19:42 +00:00
Ake Rehnman 3de6b5f6e5 jtag/drivers/stlink_usb : implemented and repaired SWIM support
Fixed a bug in stlink_usb_read_mem/write_mem preventing large data transfers

The SWIM support in stlink_usb was basically non existent so I have
implemented the missing parts. The bCBWCBLength and dCBWDataTransferLength
for STLINK-V1 protocol was not correct so that was fixed. The reason for
adding SWIM support is to add STM8 support for OpenOCD.

I have tested the driver on:
STM8 discovery board with the built-in STLINK-V1
STM8 discovery board with STLINK-V2 dongle
STM32 vldiscovery board with the built-in STLINK-V1
STM32F1xxx processor with STLINK-V2 dongle

Change-Id: I4aa80a92fb0226174356adaf2f8ff949920a621f
Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com>
Reviewed-on: http://openocd.zylin.com/3952
Tested-by: jenkins
Reviewed-by: Philipp Klaus Krause
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-12 20:17:55 +00:00
Tomas Vanek 779e95cc32 arm_adi_v5: fix regression from 4553abf906
Functions mem_ap_read() and mem_ap_write() incremented address even
if addrinc=false. I overlooked this fact and moved mem_ap_setup_tar()
set wrong addresses in no-incr mode.

Fixed by preventing address increment in no-incr mode.

Change-Id: I512e12a6a64e30cf6bc5bf77e3d57d35cc33e058
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/4326
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-01-11 08:28:29 +00:00
Megan Wachs 6f9585068f
Merge pull request #172 from riscv/dbus_read_comment
Add a comment in dbus_read
2018-01-10 15:30:56 -08:00
Tim Newsome 0d60a29c21
Merge pull request #178 from riscv/cleanup
Rename dummy variable to be correct.
2018-01-10 15:16:40 -08:00
Tim Newsome 160b794274
Merge pull request #181 from riscv/propagate_errors
Propagate register read errors
2018-01-10 15:16:19 -08:00
Tim Newsome 29c7a76708 Muck with mstatus to always be able to read FPRs
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-09 12:06:11 -08:00
Forest Crossman 6f5e9941df jtag/drivers/kitprog: Enable LOG_DEBUG_IO
Change-Id: Ic01b0acf01e18bcb2bf98c101c7b5888cdc10186
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/4323
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-09 16:22:30 +00:00
Matthias Welwarsky 3cba4bd4cb aarch64: fix crash on single-stepping
Make sure to skip un-examined targets (e.g. targets with deferred
examination) on single-stepping

fixes bug #158

Change-Id: Ib40c6fee03079fd078bd52a84615e6f8a081d128
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4184
Tested-by: jenkins
Reviewed-by: Yao Qi <qiyaoltc@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-09 09:37:14 +00:00
Tim Newsome fd506fa839 Propagate register read errors.
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
Tim Newsome 0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection
Select current hart before reading memory.
2018-01-05 14:07:38 -08:00
Tim Newsome 11e51af3b1
Merge pull request #173 from riscv/warn_names
Use register names instead of numbers in warnings
2018-01-05 13:07:08 -08:00
Tim Newsome 37434ffd77 Rename dummy variable to be correct.
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-05 13:05:33 -08:00
Tim Newsome a6b503217d
Merge pull request #174 from riscv/delay_info
Make delay update messages debug instead of info.
2018-01-05 13:03:14 -08:00
Tomas Vanek 81a33244df arm_adi_v5: reduce some CSW writes
MEM-AP access through banked data registers MEM_AP_REG_BD0..3
does not increment TAR regardless of the current autoincrement mode.
mem_ap_read_u32() and mem_ap_write_u32() can keep the current
autoincrement mode instead of switching autoincrement off.

Change-Id: Ib7ec688d3e04f1da678363cd2819ce90e8910e58
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4163
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-01-05 10:06:39 +00:00
Tomas Vanek 4553abf906 arm_adi_v5: fix wrong addressing after change of CSW_ADDRINC
Problem: If the same memory location is accessed alternatively
by MEM-AP banked data registers without autoincrement and by standard
autoincremented read/write, TAR register is not updated correctly.

How to replicate: On a Cortex-M issue
    mdw 0xe000edf0
multiple times. When poll is on (poll reads the same memory location)
only the first read is correct.
0xe000edf0: 01000000
0xe000edf0: 00000000
0xe000edf0: 20002640
0xe000edf0: 01000000
0xe000edf0: 00000000
0xe000edf0: 00000000

No problems with poll off.
0xe000edf0: 01000000
0xe000edf0: 01000000
0xe000edf0: 01000000

mem_ap_setup_tar() writes to MEM_AP_REG_TAR if requested TAR value
changed or CSW_ADDRINC_... is currently active.
However if an autoincremented access has been issued and autoinc
switched off in CSW afterwards, TAR does not get updated.

The change introduces mem_ap_update_tar_cache() which is called
after queuing of any access to MEM_AP_REG_DRW. It simulates
TAR increment to keep tar_value in sync with MEM_AP.
Crossing tar autoincrement block boundary invalidates cached value.

mem_ap_write() and mem_ap_read() do not check tar autoincrement
block boundary, mem_ap_setup_tar() is called before each transfer instead.

dap_invalidate_cache() is introduced to ensure invalidation
of all cached values during dap_dp_init() and swd_connect()

Change-Id: I815c2283d2989cffd6ea9a4100ce2f29dc3fb7b4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4162
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-01-05 10:06:30 +00:00
Tim Newsome 6f3913cedc Select current hart before reading memory.
This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).

Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04 17:12:01 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info.
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04 13:36:53 -08:00
Megan Wachs 33aad3524b
Add a comment in dbus_read
This just comments the current behavior
2018-01-04 13:27:35 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-04 13:27:18 -08:00
Bas Vermeulen ada631cc5f target aarch64: rework memory read/write to use 8/16/32 bit operations
The existing code only used Memory Access mode to read memory,
which uses 32 bit operations only.
Rework the code to check the alignment/size of the read/write operation,
and use the Memory Access mode to read aligned 32 bit memory.
When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW}
instead.

The exception handling is still the same as it was before (meaning it breaks
when things go wrong), but I can now read an 8 bit register correctly.

Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15
Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4301
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-04 09:09:46 +00:00
Tim Newsome 82529e71e0
Merge pull request #170 from riscv/strtoull
Parse 64-bit CRC addrs even on 32-bit hosts
2018-01-03 12:48:36 -08:00
Tomas Vanek bb976e3c38 jtag/drivers/cmsis-dap: fix connect under reset
Commit ef02b69b14 included
a call to cmsis_dap_cmd_DAP_Connect() before calling
cmsis_dap_cmd_DAP_SWJ_Sequence(). According to comment
it is necessary for at least Keil ULINK-ME.

Commit 72c3464be4 added
a cmsis_dap_cmd_DAP_Disconnect() before connect call to pair
connection/disconnection. It solves some problems on Atmel EDBG.

Unfortunately calling either of cmsis_dap_cmd_DAP_Connect()
or cmsis_dap_cmd_DAP_Disconnect() deasserts reset signal.
So these workarounds break ability to connect under reset.

Use cmsis_dap_cmd_DAP_Disconnect() and cmsis_dap_cmd_DAP_Connect()
pair only if both SRST and TRST are deasserted.

Change-Id: I0914dae0a1360b8c7fe48231ff3867caedfb2dbe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reported-by: Leonardo Sabino dos Santos <leonardo.sabino@gmail.com>
Reviewed-on: http://openocd.zylin.com/4100
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-03 10:56:32 +00:00
Tim Newsome 2eddd8e092 Parse 64-bit CRC addrs even on 32-bit hosts
Change-Id: I38720163eff292b2c24f25da4e25feb8245ff672
2018-01-02 12:58:46 -08:00
Tim Newsome f822956994
Merge pull request #169 from riscv/unused_boards
Remove board files that I shouldn't have added
2018-01-02 12:19:55 -08:00
Tim Newsome 1ddbe70443 Remove board files that I shouldn't have added
There are 3 other ones for the SiFive target.

Change-Id: I987331a82186a3738096cc390c91889118bf9ac2
2017-12-29 13:11:27 -08:00
Tim Newsome ab5a98663e
Merge pull request #168 from gnu-mcu-eclipse/sifive-cfg
Add config files for the SiFive boards
2017-12-29 11:39:57 -08:00
Liviu Ionescu bd566a98bc add configs for the SiFive boards
- the HiFive1 board definition includes the FTDI interface
- the Arty boards require external interface definitions
2017-12-29 17:36:54 +02:00