interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,875 Commits 69 Branches 14 Tags 92 MiB
Commit Graph

4875 Commits

Author SHA1 Message Date
Damjan Marion db91a36fdd Improve NAND flash detection 
Detect based on both manufacturer id and chip id
if manufacturer id is defined in table
 2011-05-28 14:30:58 +02:00
Damjan Marion acdf14eb43 Reorganize NAND flash table 
- added manufacturer field
- name moved to the end for better text alignment
 2011-05-28 14:27:48 +02:00
Stefan Mahr 73988aea1f mips: fix swapping if openocd is running on big endian host 2011-05-28 14:25:06 +02:00
Alan Bowman 212db44fcf Report actual current thread 2011-05-25 22:05:26 +02:00
Alan Bowman a57daf23db Add eCos/Cortex RTOS support 2011-05-25 22:05:23 +02:00
Stefan Mahr 6d6837f988 add support for spansion flash on mindspeed c300 eval board 
Signed-off-by: Stefan Mahr <stefan.mahr@sphairon.com>
 2011-05-25 22:02:40 +02:00
Spencer Oliver 5d7d08a1f0 dsp5680xx: whitespace cleanup 
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
 2011-05-23 10:23:34 +01:00
Spencer Oliver d16b0ea6d4 Fix build issue under cygwin 
cygwin does not define sleep, so use our internal win32 version.
caused by commit 9d4aec6bda

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
 2011-05-23 10:22:12 +01:00
Rodrigo L. Rosa ef599aebfd flashing speed improved using queued jtag. error propagation improved. 2011-05-19 07:27:02 +02:00
Jie Zhang ee124401a2 Get register value if it's invalid in cache. 2011-05-18 18:52:20 +02:00
Alan Bowman 6d9f61fb65 Corrected test for invalid current_threadid 2011-05-18 18:51:10 +02:00
Rodrigo L. Rosa 129f099ef1 flash support (only full erase/write) for 568013 and 568037 2011-05-18 18:47:55 +02:00
Rodrigo L. Rosa 9d4aec6bda partial support for 568013 and 568037, target integration. 2011-05-18 18:47:50 +02:00
Alan Bowman 6349a47ebc Correct stacking direction and use of address offset 2011-05-14 16:59:29 +02:00
Michel Jaouen 53c0fb6ef5 cortex a : smp doc update 2011-05-09 21:50:44 +02:00
Øyvind Harboe 289cecebf0 beagleboard: add support for various icepick versions 
The beagleboard icepick jtag tap id's vary.
 2011-05-05 15:47:12 +02:00
Jonas Hoerberg 2889471b58 at91rm9200-ek: add low default communication speed 2011-05-05 15:43:37 +02:00
Alexandre Pereira da Silva 522d5b84e2 Add support for the lpc2460 target 2011-05-03 22:07:01 +02:00
Alexandre Pereira da Silva 743fada06a Make the lpc2xxx generic driver support romless parts 2011-05-03 22:06:57 +02:00
Jie Zhang 7d8053e93f Remove useless MIPS code in avr32_ap7k.c. 2011-05-03 21:59:08 +02:00
Jonas Hörberg e3f3f60a02 adapter speed: require init script setting and centralize activation from drivers to core.c 
Signed-off-by: Jonas Hörberg <jhorberg@sauer-danfoss.com>
 2011-05-01 00:38:04 +02:00
Øyvind Harboe 5c739b148e ecos: add 64 bit types for sprintf/sscanf 2011-04-28 22:17:48 +02:00
Michel Jaouen d2911627d2 u8500.cfg : ste u8500 support 2011-04-28 12:22:47 +02:00
Michel Jaouen 1e7e594452 gdb_server : 'R' command replied by OK 2011-04-28 12:22:39 +02:00
Michel Jaouen 5578935eff cortex_a : smp support 
Conflicts:

	src/target/cortex_a.c
 2011-04-28 12:22:29 +02:00
Michel Jaouen b778b36f29 smp : infra for smp minimum support 2011-04-28 12:22:10 +02:00
Øyvind Harboe 36d60ee6c8 cfi: leave check on whether target is running to target_write_memory() 
there was a check in clearing the status register that
called exit() if the target was running. target_write_memory()
has such a check and will report the error correctly.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
 2011-04-27 23:02:28 +02:00
SimonQian 5bd1f0bad4 add STM32F2 revY 2011-04-26 12:05:07 +02:00
SimonQian 2e88162b00 remove read of flash_size in STM32F2 2011-04-26 12:04:57 +02:00
Damjan Marion 5d987bca9c buspirate: fix building on some OSes 2011-04-26 11:55:54 +02:00
Michel Jaouen 3c6af518b3 rtos : compilation error on amd64 2011-04-19 12:53:56 +02:00
Alexandre Pereira da Silva 32ede8fa21 Fix non cfi x16 nor flash connected to x8 bus. The ids in the table should be masked before comparison. 2011-04-19 12:53:05 +02:00
Alexandre Pereira da Silva e105915a4a Make the LPC32xx nand driver support up to 5 address cycles. This will only work in the SLC driver. 2011-04-19 12:51:49 +02:00
Alexandre Pereira da Silva 2ed19d3b9b Make the LPC32xx slc nand driver the default 2011-04-19 12:51:36 +02:00
Øyvind Harboe e984dc1f16 jtag: clarify jtag->init() and jtag->quit() definitions 
only set jtag global pointer if jtag->init() succeeds. Less code,
more clear what the rules are.

Fix nit that error value from init() was not propagated unmodified.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
 2011-04-19 12:43:16 +02:00
Broadcom Corporation (Evan Hunter) b69119668e RTOS Thread awareness support wip 
- works on Cortex-M3 with ThreadX and FreeRTOS

Compared to original patch a few nits were fixed:

- remove stricmp usage
- unsigned compare fix
- printf formatting fixes
- fixed a bug with overrunning a memory buffer allocated with malloc.
 2011-04-15 08:24:18 +02:00
Spencer Oliver f9feeacb7f pic32: update pic32mx flash driver 
Update devices as per the latest programming manual.

We now use the full DEVID to identify the target. Previously we used
a 8bit id but that has now been changed in the manual.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
 2011-04-14 09:17:17 +01:00
Luca Ellero ecd5e5de7f Replace byte-access to memory with faster word-access 
Freescale iMX53 doesn't seem to like unaligned accesses to his memory
mapped registers.
Anyway this patch makes dump_image/load_image 4X faster for every
access through APB.

Signed-off-by: Luca Ellero <lroluk@gmail.com>
 2011-04-13 21:33:11 +02:00
Luca Ellero 81f238f522 Add opcodes for load/store registers words immediate post-indexed 
Signed-off-by: Luca Ellero <lroluk@gmail.com>
 2011-04-13 21:32:24 +02:00
Luca Ellero 041953f3b1 Add preliminary support for Freescale iMX53 
Signed-off-by: Luca Ellero <lroluk@gmail.com>
 2011-04-13 21:32:00 +02:00
Alexandre Pereira da Silva 5cc83a880a Add the REV A tap id to the LPC3250 configuration 2011-04-13 21:28:44 +02:00
Michel JAOUEN 08303f10aa cortex_a :apb mem read/write working with mmu_on 
Conflicts:

	src/target/cortex_a.c
 2011-04-13 10:57:02 +02:00
Michel JAOUEN 28ddd16ddc cortex_a : multiple target on the same dap 2011-04-13 10:56:52 +02:00
Michel JAOUEN a7844aa4e8 cortex_a : use dap ref from armv4_5common 2011-04-13 10:56:42 +02:00
Jean-Christophe PLAGNIOL-VILLARD d6027ca6a8 at91: add at91sam9263 chip register definition 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
 2011-04-09 19:19:36 +02:00
Jean-Christophe PLAGNIOL-VILLARD ba71e8c521 at91: add chip register definition and generic init support 
for
 - pio
 - pmc
 - rstc
 - wdt
 - sdramc
 - smc

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
 2011-04-09 19:18:03 +02:00
Jean-Christophe PLAGNIOL-VILLARD 28e6dcee85 add at91sam9263-ek support 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
 2011-04-09 10:16:28 +02:00
Jean-Christophe PLAGNIOL-VILLARD 22437fac28 add at91sam9261-ek support 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
 2011-04-09 10:14:46 +02:00
Jean-Christophe PLAGNIOL-VILLARD 5d538084be at91: add at91sam9261 chip register definition 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
 2011-04-09 10:13:59 +02:00
Jean-Christophe PLAGNIOL-VILLARD 13cf987bb8 jlink: jlink_debug_buffer use inline function when _DEBUG_USB_COMMS_ not define 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
 2011-04-09 10:12:08 +02:00