u8500.cfg : ste u8500 support
This commit is contained in:
Michel Jaouen
Øyvind Harboe
parent
1e7e594452
commit
d2911627d2
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# Copyright (C) ST-Ericsson SA 2011
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# Author : michel.jaouen@stericsson.com
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# U8500 target
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proc mmu_off {} {
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set cp [arm mrc 15 0 1 0 0]
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set cp [expr ($cp & ~1)]
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arm mcr 15 0 1 0 0 $cp
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}
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proc mmu_on {} {
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set cp [arm mrc 15 0 1 0 0]
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set cp [expr ($cp | 1)]
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arm mcr 15 0 1 0 0 $cp
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}
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proc ocd_gdb_restart {target_id} {
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global _TARGETNAME_1
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global _SMP
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targets $_TARGETNAME_1
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if { [expr ($_SMP == 1)] } {
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cortex_a8 smp_off
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}
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rst_run
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halt
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if { [expr ($_SMP == 1)]} {
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cortex_a8 smp_on
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}
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}
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proc smp_reg {} {
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global _TARGETNAME_1
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global _TARGETNAME_2
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targets $_TARGETNAME_1
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echo "$_TARGETNAME_1"
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set pc1 [reg pc]
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set stck1 [reg sp_svc]
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targets $_TARGETNAME_2
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echo "$_TARGETNAME_1"
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set pc2 [reg pc]
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set stck2 [reg sp_svc]
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}
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proc u8500_tapenable {chip val} {
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echo "JTAG tap enable $chip"
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}
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proc pwrsts { } {
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global _CHIPNAME
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irscan $_CHIPNAME.jrc 0x3a
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drscan $_CHIPNAME.jrc 4 0
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set pwrsts [drscan $_CHIPNAME.jrc 16 0]
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echo "pwrsts ="$pwrsts
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set a9 [expr (0x$pwrsts & 0xc)]
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set ape [expr (0x$pwrsts & 0x3)]
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if {[string equal "0" $ape]} {
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echo "ape off"
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} else {
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echo "ape on"
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}
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echo "$a9"
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switch $a9 {
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4 {
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echo "A9 in retention"
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}
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8 {
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echo "A9 100% DVFS"
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}
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c {
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echo "A9 50% DVFS"
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}
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}
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}
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proc poll_pwrsts { } {
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global _CHIPNAME
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set result 1
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set i 0
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irscan $_CHIPNAME.jrc 0x3a
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drscan $_CHIPNAME.jrc 4 0
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set pwrsts [drscan $_CHIPNAME.jrc 16 0]
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set pwrsts [expr (0x$pwrsts & 0xc)]
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while {[string equal "4" $pwrsts] && $i<20} {
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irscan $_CHIPNAME.jrc 0x3a
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drscan $_CHIPNAME.jrc 4 0;
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set pwrsts [drscan $_CHIPNAME.jrc 16 0]
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set pwrsts [expr (0x$pwrsts & 0xc)]
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if {![string equal "4" $pwrsts]} {
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set result 1
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} else {
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set result 0
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sleep 200
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echo "loop $i"
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}
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incr i
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}
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return $result
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}
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proc halt_ { } {
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if {[poll_pwrsts]==1} {
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halt
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} else {
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echo "halt failed : target in retention"
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}
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}
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proc u8500_dapenable {chip} {
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}
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proc u8500_tapdisable {chip val} {
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echo "JTAG tap disable $chip"
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}
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proc enable_apetap {} {
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global _CHIPNAME
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global _TARGETNAME_2
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global _TARGETNAME_1
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poll off
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irscan $_CHIPNAME.jrc 0x3e
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drscan $_CHIPNAME.jrc 8 0xcf
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jtag tapenable $_CHIPNAME.dap
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irscan $_CHIPNAME.jrc 0x6
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drscan $_CHIPNAME.jrc 32 0
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irscan $_CHIPNAME.jrc 0x6
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drscan $_CHIPNAME.jrc 32 0
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set status [$_TARGETNAME_1 curstate]
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if {[string equal "unknown" $status]} {
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$_TARGETNAME_1 arp_examine
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}
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set status [$_TARGETNAME_2 curstate]
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if {[string equal "unknown" $status]} {
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$_TARGETNAME_2 arp_examine
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}
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}
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tcl_port 5555
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telnet_port 4444
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gdb_port 3333
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if { [info exists CHIPNAME] } {
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global _CHIPNAME
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set _CHIPNAME $CHIPNAME
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} else {
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global _CHIPNAME
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set _CHIPNAME u8500
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# this defaults to a bigendian
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set _ENDIAN little
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}
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# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT,
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
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jtag configure $_CHIPNAME.dap -event tap-enable \
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"u8500_dapenable $_CHIPNAME.dap"
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jtag configure $_CHIPNAME.dap -event tap-disable \
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"u8500_tapdisable $_CHIPNAME.dap 0xc0"
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#CLTAPC TAP JRC equivalent
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if { [info exists CLTAPC_ID ] } {
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set _CLTAPC_ID $CLTAPC_ID
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} else {
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set _CLTAPC_ID 0x22286041
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version
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if { ![info exists TARGETNAME_1 ] } {
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global _TARGETNAME_1
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set _TARGETNAME_1 $_CHIPNAME.cpu1
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} else {
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global _TARGETNAME_1
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set _TARGETNAME_1 $TARGETNAME_1
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}
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if { [info exists DAP_DBG1] } {
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set _DAP_DBG1 $DAP_DBG1
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} else {
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set _DAP_DBG1 0x801A8000
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}
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if { [info exists DAP_DBG2] } {
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set _DAP_DBG2 $DAP_DBG2
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} else {
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set _DAP_DBG2 0x801AA000
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}
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target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0
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$_TARGETNAME_1 configure -event gdb-attach {
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halt
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}
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if { ![info exists TARGETNAME_2 ] } {
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global _TARGETNAME_2
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set _TARGETNAME_2 $_CHIPNAME.cpu2
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} else {
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global _TARGETNAME_2
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set _TARGETNAME_2 $TARGETNAME_2
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}
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target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1
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$_TARGETNAME_2 configure -event gdb-attach {
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halt
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}
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if {![info exists SMP]} {
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global _SMP
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set _SMP 1
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} else {
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global _SMP
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set _SMP $SMP
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}
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global SMP
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if { $_SMP == 1} {
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target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
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}
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proc secsts1 { } {
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global _CHIPNAME
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irscan $_CHIPNAME.jrc 0x3a
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drscan $_CHIPNAME.jrc 4 4
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set secsts1 [drscan $_CHIPNAME.jrc 16 0]
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echo "secsts1 ="$secsts1
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set secsts1 [expr (0x$secsts1 & 0x4)]
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if {![string equal "4" $secsts1]} {
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echo "APE target secured"
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} else {
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echo "APE target not secured"
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}
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}
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proc att { } {
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global _CHIPNAME
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jtag arp_init
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irscan $_CHIPNAME.jrc 0x3a
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drscan $_CHIPNAME.jrc 4 4
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set secsts1 [drscan $_CHIPNAME.jrc 16 0]
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echo "secsts1 ="$secsts1
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set secsts1 [expr (0x$secsts1 & 0x4)]
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if {[string equal "4" $secsts1]} {
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if {[poll_pwrsts]==1} {
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enable_apetap
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} else {
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echo "target in retention"
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}
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} else {
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echo "target secured"
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}
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}
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proc rst_run { } {
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global _CHIPNAME
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global _TARGETNAME_2
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global _TARGETNAME_1
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set status [$_TARGETNAME_1 curstate]
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if {[string equal "halted" $status]} {
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resume
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targets $_TARGETNAME_1
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}
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set status [$_TARGETNAME_2 curstate]
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if {[string equal "halted" $status]} {
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resume
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targets $_TARGETNAME_2
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}
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poll off
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jtag arp_init
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reset
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sleep 20
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irscan $_CHIPNAME.jrc 0x3a
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drscan $_CHIPNAME.jrc 4 4
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set secsts1 [drscan $_CHIPNAME.jrc 16 0]
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echo "secsts1 ="$secsts1
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set secsts1 [expr (0x$secsts1 & 0x4)]
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while {![string equal "4" $secsts1]} {
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irscan u8500.jrc 0x3a
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drscan u8500.jrc 4 4
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set secsts1 [drscan $_CHIPNAME.jrc 16 0]
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echo "secsts1 ="$secsts1
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set secsts1 [expr (0x$secsts1 & 0x4)]
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}
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echo "ape debugable"
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enable_apetap
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poll on
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targets $_TARGETNAME_1
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dap apsel 1
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}
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if {![info exists MAXSPEED]} {
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global _MAXSPEED
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set _MAXSPEED 15000
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} else {
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global _MAXSPEED
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set _MAXSPEED $MAXSPEED
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}
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global _MAXSPEED
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adapter_khz $_MAXSPEED
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gdb_breakpoint_override hard
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set mem inaccessible-by-default-off
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jtag_ntrst_delay 100
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reset_config trst_and_srst combined
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